7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}_interrupt.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
200 pname
, ps
, n
, fname
):
202 ck
= self
.get_clock_reset(name
, count
)
204 if ck
== PBase
.get_clock_reset(self
, name
, count
):
205 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
206 .format(ps
, n
, fname
))
208 n2
= "{0}{1}".format(name
, count
)
209 sync
= '{0}_{1}_sync'.format(n2
, pname
)
210 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
212 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
213 .format(sync
, n
, fname
))
214 elif ctype
== 'outen':
215 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
218 if ck
== PBase
.get_clock_reset(self
, name
, count
):
219 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
222 n2
= "{0}{1}".format(name
, count
)
223 sync
= '{0}_{1}_sync'.format(n2
, pname
)
224 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
226 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
230 def mk_clk_con(self
, name
, count
):
232 ck
= self
.get_clock_reset(name
, count
)
233 if ck
== PBase
.get_clock_reset(self
, name
, count
):
235 spc
= "sp_clock, sp_reset"
237 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
239 for p
in self
.peripheral
.pinspecs
:
243 if typ
== 'out' or typ
== 'inout':
244 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
245 n_
= "{0}{1}".format(n
, count
)
248 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
249 if typ
== 'in' or typ
== 'inout':
250 #fname = self.pinname_in(pname)
251 n_
= "{0}{1}".format(n
, count
)
252 n_
= '{0}_{1}'.format(n_
, pname
)
253 #n_ = self.ifname_tweak(pname, 'in', n_)
254 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
255 return '\n'.join(ret
)
258 def mk_cellconn(self
, *args
):
261 def mkfast_peripheral(self
, size
=0):
264 def mkslow_peripheral(self
, size
=0):
267 def mksuffix(self
, name
, i
):
270 def __mk_connection(self
, con
, aname
, fabricname
):
271 txt
= "mkConnection ({2}.v_to_slaves\n" + \
272 " [fromInteger(valueOf({1}))],\n" + \
275 print "PBase __mk_connection", self
.name
, aname
278 return txt
.format(con
, aname
, fabricname
)
280 def __mk_master_connection(self
, con
, aname
):
281 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
282 " [fromInteger(valueOf({1}))],\n" + \
285 print "PBase __mk_connection", self
.name
, aname
288 return txt
.format(con
, aname
)
290 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
293 print "PBase mk_conn", self
.name
, count
294 aname
= self
.axi_slave_name(name
, count
, typ
)
295 #dname = self.mksuffix(name, count)
296 #dname = "{0}{1}".format(name, dname)
297 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
298 return self
.__mk
_connection
(con
, aname
, fabricname
)
300 def _mk_connection(self
, name
=None, count
=0):
303 def pinname_out(self
, pname
):
306 def pinname_in(self
, pname
):
309 def pinname_outen(self
, pname
):
312 def ifname_tweak(self
, pname
, typ
, txt
):
315 def pinname_tweak(self
, pname
, typ
, txt
):
321 def mk_plic(self
, inum
, irq_offs
):
323 print "mk_plic", self
.name
, inum
, irq_offs
324 niq
= self
.num_irqs()
326 return ('', irq_offs
)
327 name
= self
.get_iname(inum
)
328 res
.append("// PLIC rules for {0}".format(name
))
329 for idx
in range(niq
):
330 plic_obj
= self
.plic_object(name
, idx
)
331 print "plic_obj", name
, idx
, plic_obj
332 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
334 irq_offs
+= 1 # increment to next irq
335 return ('\n'.join(res
), irq_offs
)
337 def mk_ext_ifacedef(self
, iname
, inum
):
340 def extfastifinstance(self
, name
, count
):
343 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
347 pname
= self
.get_iname(count
)
351 sname
= self
.peripheral
.iname().format(count
)
352 template
= "interface {0}{3} = {2}{1}{4};"
353 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
355 def extifinstance2(self
, name
, count
):
358 def extifinstance(self
, name
, count
):
359 return self
._extifinstance
(name
, count
, "",
360 "pinmux.peripheral_side.")
364 rule rl_connect_{0}_to_plic_{2};
365 if({1} == 1'b1) begin
366 ff_gateway_queue[{2}].enq(1);
367 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
372 axi_master_declarations
= """\
373 typedef 0 Dmem_master_num;
374 typedef 1 Imem_master_num;
376 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
378 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
380 typedef TAdd#(DMA_master_num,1)
384 axi_fastslave_declarations
= """\
386 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
387 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
389 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
391 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
393 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
395 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
397 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
398 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
400 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
403 axi_slave_declarations
= """\
404 typedef 0 SlowMaster;
406 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
408 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
410 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
412 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
415 pinmux_cellrule
= """\
416 rule connect_select_lines_pinmux;
422 class CallFn(object):
423 def __init__(self
, peripheral
, name
):
424 self
.peripheral
= peripheral
427 def __call__(self
, *args
):
428 #print "__call__", self.name, self.peripheral.slow, args
429 if not self
.peripheral
.slow
:
431 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
434 class PeripheralIface(object):
435 def __init__(self
, ifacename
):
437 slow
= slowfactory
.getcls(ifacename
)
438 print "Iface", ifacename
, slow
440 self
.slow
= slow(ifacename
)
441 self
.slow
.peripheral
= self
442 for fname
in ['slowimport',
444 'extifinstance2', 'extifinstance', 'extifdecl',
445 'slowifdecl', 'slowifdeclmux',
448 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
450 'mk_plic', 'mk_ext_ifacedef',
451 'mk_clk_con', 'mk_ext_ifacedef',
452 'mk_connection', 'mk_cellconn', '_mk_pincon']:
453 fn
= CallFn(self
, fname
)
454 setattr(self
, fname
, types
.MethodType(fn
, self
))
456 #print "PeripheralIface"
459 def mksuffix(self
, name
, i
):
460 if self
.slow
is None:
462 return self
.slow
.mksuffix(name
, i
)
464 def axi_reg_def(self
, start
, count
):
467 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
469 def axi_master_idx(self
, start
, count
, typ
):
470 if not self
.slow
or not self
.slow
.has_axi_master():
472 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
474 def axi_slave_idx(self
, start
, count
, typ
):
477 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
479 def axi_fastaddr_map(self
, count
):
482 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
484 def axi_addr_map(self
, count
):
487 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
490 class PeripheralInterfaces(object):
492 self
.fastbusmode
= False
494 def slowimport(self
, *args
):
496 for (name
, count
) in self
.ifacecount
:
497 #print "slowimport", name, self.data[name].slowimport
498 ret
.append(self
.data
[name
].slowimport())
499 return '\n'.join(li(list(filter(None, ret
)), 4))
501 def extfastifinstance(self
, *args
):
503 for (name
, count
) in self
.ifacecount
:
504 for i
in range(count
):
505 iname
= self
.data
[name
].iname().format(i
)
506 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
507 if self
.is_on_fastbus(name
, i
):
509 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
510 return '\n'.join(li(list(filter(None, ret
)), 8))
512 def extifinstance2(self
, *args
):
514 for (name
, count
) in self
.ifacecount
:
515 for i
in range(count
):
516 iname
= self
.data
[name
].iname().format(i
)
517 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
518 return '\n'.join(li(list(filter(None, ret
)), 8))
520 def extifinstance(self
, *args
):
522 for (name
, count
) in self
.ifacecount
:
523 for i
in range(count
):
524 iname
= self
.data
[name
].iname().format(i
)
525 if not self
.is_on_fastbus(name
, i
):
527 ret
.append(self
.data
[name
].extifinstance(name
, i
))
528 return '\n'.join(li(list(filter(None, ret
)), 8))
530 def extifdecl(self
, *args
):
532 for (name
, count
) in self
.ifacecount
:
533 for i
in range(count
):
534 if not self
.is_on_fastbus(name
, i
):
536 ret
.append(self
.data
[name
].extifdecl(name
, i
))
537 return '\n'.join(li(list(filter(None, ret
)), 8))
539 def slowifdeclmux(self
, *args
):
541 for (name
, count
) in self
.ifacecount
:
542 for i
in range(count
):
543 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
544 return '\n'.join(li(list(filter(None, ret
)), 8))
546 def fastifdecl(self
, *args
):
548 for (name
, count
) in self
.ifacecount
:
549 for i
in range(count
):
550 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
551 if self
.is_on_fastbus(name
, i
):
553 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
554 return '\n'.join(li(list(filter(None, ret
)), 4))
556 def slowifdecl(self
, *args
):
558 for (name
, count
) in self
.ifacecount
:
559 for i
in range(count
):
560 if self
.is_on_fastbus(name
, i
):
562 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
563 return '\n'.join(list(filter(None, ret
)))
565 def axi_fastmem_def(self
, *args
):
566 return self
._axi
_reg
_def
(0x50000000, *args
)
568 def axi_reg_def(self
, *args
):
569 return self
._axi
_reg
_def
(0x00011100, *args
)
571 def _axi_reg_def(self
, start
, *args
):
573 for (name
, count
) in self
.ifacecount
:
574 for i
in range(count
):
575 if self
.is_on_fastbus(name
, i
):
577 x
= self
.data
[name
].axi_reg_def(start
, i
)
578 #print ("ifc", name, x)
582 return '\n'.join(list(filter(None, ret
)))
584 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
586 for (name
, count
) in self
.ifacecount
:
587 for i
in range(count
):
588 if self
.is_on_fastbus(name
, i
):
591 fn
= self
.data
[name
].axi_master_idx
593 fn
= self
.data
[name
].axi_slave_idx
594 (rdef
, offs
) = fn(start
, i
, idxtype
)
595 #print ("ifc", name, rdef, offs)
598 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
599 decls
= '\n'.join(list(filter(None, ret
)))
600 return template
.format(decls
)
602 def axi_slave_idx(self
, *args
):
603 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
606 def axi_fastslave_idx(self
, *args
):
607 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
610 def axi_master_idx(self
, *args
):
611 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
614 def axi_fastslave_idx(self
, *args
):
615 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
618 def axi_fastaddr_map(self
, *args
):
620 for (name
, count
) in self
.ifacecount
:
621 for i
in range(count
):
622 if self
.is_on_fastbus(name
, i
):
624 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
625 return '\n'.join(li(list(filter(None, ret
)), 8))
627 def axi_addr_map(self
, *args
):
629 for (name
, count
) in self
.ifacecount
:
630 for i
in range(count
):
631 if self
.is_on_fastbus(name
, i
):
633 ret
.append(self
.data
[name
].axi_addr_map(i
))
634 return '\n'.join(li(list(filter(None, ret
)), 8))
636 def mkfast_peripheral(self
, *args
):
638 for (name
, count
) in self
.ifacecount
:
639 for i
in range(count
):
640 if self
.is_on_fastbus(name
, i
):
642 #print "mkfast", name, count
643 x
= self
.data
[name
].mkfast_peripheral()
645 suffix
= self
.data
[name
].mksuffix(name
, i
)
646 ret
.append(x
.format(suffix
))
647 return '\n'.join(li(list(filter(None, ret
)), 8))
649 def mkslow_peripheral(self
, *args
):
651 for (name
, count
) in self
.ifacecount
:
652 for i
in range(count
):
653 if self
.is_on_fastbus(name
, i
):
655 #print "mkslow", name, count
656 x
= self
.data
[name
].mkslow_peripheral()
658 suffix
= self
.data
[name
].mksuffix(name
, i
)
659 ret
.append(x
.format(suffix
))
660 return '\n'.join(li(list(filter(None, ret
)), 8))
662 def mk_fast_connection(self
, *args
):
664 for (name
, count
) in self
.ifacecount
:
665 for i
in range(count
):
666 if self
.is_on_fastbus(name
, i
):
668 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
671 print self
.data
[name
].mk_connection
673 return '\n'.join(li(list(filter(None, ret
)), 12))
675 def mk_connection(self
, *args
):
677 for (name
, count
) in self
.ifacecount
:
678 for i
in range(count
):
679 if self
.is_on_fastbus(name
, i
):
681 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
684 print self
.data
[name
].mk_connection
686 return '\n'.join(li(list(filter(None, ret
)), 8))
688 def mk_cellconn(self
):
691 for (name
, count
) in self
.ifacecount
:
692 for i
in range(count
):
693 if self
.is_on_fastbus(name
, i
):
695 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
698 (txt
, cellcount
) = res
700 ret
= li('\n'.join(list(filter(None, ret
))), 4)
701 return li(pinmux_cellrule
.format(ret
), 4)
704 return self
._mk
_pincon
("slow")
706 def mk_fast_pincon(self
):
707 return self
._mk
_pincon
("fast")
709 def _mk_pincon(self
, typ
):
711 for (name
, count
) in self
.ifacecount
:
712 for i
in range(count
):
713 if self
.is_on_fastbus(name
, i
):
715 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
717 return '\n'.join(li(list(filter(None, ret
)), 4))
719 def mk_dma_irq(self
):
727 for (name
, count
) in self
.ifacecount
:
729 for i
in range(count
):
730 if not self
.is_on_fastbus(name
, i
):
732 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
736 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
737 ifacerules
.append(txt
)
738 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
740 ifacerules
= list(filter(None, ifacerules
))
742 txt
= "rule synchronize_%s_interrupts;" % name
745 rules
.append("endrule")
747 cnct
= list(filter(None, cnct
))
749 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
750 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
753 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
755 cnct
.append(" dma.interrupt_from_peripherals(\n" +
756 " lv_interrupt_to_DMA);")
757 cnct
.append("endrule;")
759 ret
= list(filter(None, sync
+ rules
+ cnct
))
761 return '\n'.join(ret
)
763 def num_dmachannels(self
):
764 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
766 def mk_ext_ifacedef(self
):
768 for (name
, count
) in self
.ifacecount
:
769 for i
in range(count
):
770 if self
.is_on_fastbus(name
, i
):
772 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
774 return '\n'.join(li(list(filter(None, ret
)), 8))
778 irq_offs
= 8 # XXX: DMA scovers 0-7?
779 for (name
, count
) in self
.ifacecount
:
780 for i
in range(count
):
781 if self
.is_on_fastbus(name
, i
):
783 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
786 (txt
, irq_offs
) = res
788 self
.num_slow_irqs
= irq_offs
789 return '\n'.join(li(list(filter(None, ret
)), 4))
791 def mk_sloirqsdef(self
):
792 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
794 def mk_clk_con(self
):
796 for (name
, count
) in self
.ifacecount
:
797 for i
in range(count
):
798 if self
.is_on_fastbus(name
, i
):
800 txt
= self
.data
[name
].mk_clk_con(name
, i
)
802 return '\n'.join(li(list(filter(None, ret
)), 8))
804 def is_on_fastbus(self
, name
, i
):
805 #print "fastbus mode", self.fastbusmode, name, i
806 iname
= self
.data
[name
].iname().format(i
)
808 return iname
not in self
.fastbus
809 return iname
in self
.fastbus
812 class PFactory(object):
813 def getcls(self
, name
):
814 from uart
import uart
815 from quart
import quart
816 from sdmmc
import sdmmc
818 from eint
import eint
819 from rs232
import rs232
821 from eint
import eint
822 from jtag
import jtag
823 from spi
import spi
, mspi
824 from qspi
import qspi
, mqspi
825 from gpio
import gpio
826 from rgbttl
import rgbttl
827 from flexbus
import flexbus
829 for k
, v
in {'uart': uart
,
845 if name
.startswith(k
):
850 slowfactory
= PFactory()
852 if __name__
== '__main__':
856 i
= PeripheralIface('uart')
858 i
= PeripheralIface('gpioa')