7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
, idx
):
90 return "%(name)s%(ifacenum)d%(idx)sBase" % locals()
92 def axiend(self
, name
, ifacenum
, idx
):
94 return "%(name)s%(ifacenum)d%(idx)sEnd" % locals()
96 def _axi_reg_def(self
, idx
, numregs
, start
, name
, ifacenum
):
98 offs
= numregs
* 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
, idx
)
103 bend
= self
.axiend(name
, ifacenum
, idx
)
104 comment
= "%d 32-bit regs" % numregs
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_reg_def(self
, start
, name
, ifacenum
):
110 offs
= self
.num_axi_regs32()
113 if not isinstance(offs
, list):
118 for (idx
, nregs
) in enumerate(offs
):
123 (txt
, off
) = self
._axi
_reg
_def
(idx
, nregs
, start
, name
, ifacenum
)
127 return ('\n'.join(res
), offstotal
)
129 def axi_master_name(self
, name
, ifacenum
, typ
=''):
131 return "{0}{1}_master_num".format(name
, ifacenum
)
133 def axi_slave_name(self
, idx
, name
, ifacenum
, typ
=''):
135 return "{0}{1}{3}_{2}slave_num".format(name
, ifacenum
, typ
, idx
)
137 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
138 name
= self
.axi_master_name(name
, ifacenum
, typ
)
139 return ("typedef {0} {1};".format(idx
, name
), 1)
141 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
142 offs
= self
.num_axi_regs32()
145 if not isinstance(offs
, list):
148 for (i
, nregs
) in enumerate(offs
):
153 name_
= self
.axi_slave_name(idx_
, name
, ifacenum
, typ
)
154 res
.append("typedef {0} {1};".format(idx
+i
, name_
))
155 return ('\n'.join(res
), len(offs
))
157 def axi_fastaddr_map(self
, name
, ifacenum
):
158 return self
.axi_addr_map(name
, ifacenum
, 'fast')
160 def _axi_addr_map(self
, idx
, name
, ifacenum
, typ
=""):
161 bname
= self
.axibase(name
, ifacenum
, idx
)
162 bend
= self
.axiend(name
, ifacenum
, idx
)
163 name
= self
.axi_slave_name(idx
, name
, ifacenum
, typ
)
165 if(addr>=`{0} && addr<=`{1})
166 return tuple2(True,fromInteger(valueOf({2})));
168 return template
.format(bname
, bend
, name
)
170 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
171 offs
= self
.num_axi_regs32()
174 if not isinstance(offs
, list):
177 for (idx
, nregs
) in enumerate(offs
):
182 res
.append(self
._axi
_addr
_map
(idx
, name
, ifacenum
, typ
))
183 return '\n'.join(res
)
185 def _mk_pincon(self
, name
, count
, ptyp
):
186 # TODO: really should be using bsv.interface_decl.Interfaces
187 # pin-naming rules.... logic here is hard-coded to duplicate
188 # it (see Interface.__init__ outen)
190 for p
in self
.peripheral
.pinspecs
:
193 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
194 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
195 ret
.append("//%s %s" % (n
, str(p
)))
197 sname
= self
.get_iname(count
)
198 sname
= "{0}.{1}".format(sname
, pname
)
199 ps
= "slow_peripherals.%s" % sname
201 sname
= self
.peripheral
.iname().format(count
)
202 sname
= "{0}.{1}".format(sname
, pname
)
203 ps
= "pinmux.peripheral_side.%s" % sname
204 if typ
== 'out' or typ
== 'inout':
205 fname
= self
.pinname_out(pname
)
206 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
207 n_
= "{0}{1}".format(n
, count
)
215 cn
= self
._mk
_actual
_connection
('out', name
,
217 pname
, ps_
, n_
, fname
)
221 fname
= self
.pinname_outen(pname
)
223 if isinstance(fname
, str):
224 fname
= "{0}.{1}".format(n_
, fname
)
225 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
226 cn
= self
._mk
_actual
_connection
('outen', name
,
230 if typ
== 'in' or typ
== 'inout':
231 fname
= self
.pinname_in(pname
)
237 n_
= "{0}{1}".format(n
, count
)
238 n_
= '{0}.{1}'.format(n_
, fname
)
239 n_
= self
.ifname_tweak(pname
, 'in', n_
)
240 cn
= self
._mk
_actual
_connection
('in', name
,
242 pname
, ps_
, n_
, fname
)
244 return '\n'.join(ret
)
246 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
250 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
252 sname
= self
.get_iname(count
)
253 ps
= "slow_peripherals.%s" % sname
255 sname
= self
.peripheral
.iname().format(count
)
256 ps
= "pinmux.peripheral_side.%s" % sname
257 n
= self
.get_iname(count
)
259 n
= "{0}.{1}".format(n
, stype
)
260 ps_
= "{0}.{1}".format(ps
, pname
)
261 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
262 pname
, ps_
, n
, stype
)
263 return '\n'.join(ret
)
265 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
266 pname
, ps
, n
, fname
):
268 ck
= self
.get_clock_reset(name
, count
)
270 if ck
== PBase
.get_clock_reset(self
, name
, count
):
271 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
272 .format(ps
, n
, fname
))
274 n2
= "{0}{1}".format(name
, count
)
275 sync
= '{0}_{1}_sync'.format(n2
, pname
)
276 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
278 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
279 .format(sync
, n
, fname
))
280 elif ctype
== 'outen':
281 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
284 if ck
== PBase
.get_clock_reset(self
, name
, count
):
285 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
288 n2
= "{0}{1}".format(name
, count
)
289 sync
= '{0}_{1}_sync'.format(n2
, pname
)
290 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
292 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
297 def _mk_clk_con(self
, name
, count
, ctype
):
299 ck
= self
.get_clock_reset(name
, count
)
300 if ck
== PBase
.get_clock_reset(self
, name
, count
):
303 spc
= self
.get_clk_spc(ctype
)
306 ck
= self
.get_clk_spc(ctype
)
308 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
310 for p
in self
.peripheral
.pinspecs
:
314 if typ
== 'out' or typ
== 'inout':
315 fname
= self
.pinname_out(pname
)
318 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
319 n_
= "{0}{1}".format(n
, count
)
322 n_
= '{0}_{1}'.format(n_
, pname
)
323 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
324 if typ
== 'in' or typ
== 'inout':
325 fname
= self
.pinname_in(pname
)
328 #fname = self.pinname_in(pname)
329 n_
= "{0}{1}".format(n
, count
)
330 n_
= '{0}_{1}'.format(n_
, pname
)
331 #n_ = self.ifname_tweak(pname, 'in', n_)
332 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
333 return '\n'.join(ret
)
335 def get_clk_spc(self
, ctype
):
337 return "sp_clock, sp_reset"
339 return "core_clock, core_reset"
341 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
342 ck
= self
.get_clock_reset(name
, count
)
343 if ck
== PBase
.get_clock_reset(self
, name
, count
):
346 spc
= self
.get_clk_spc(ctype
)
349 ck
= self
.get_clk_spc(ctype
)
351 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
354 n_
= "{0}{1}".format(name
, count
)
355 n_
= '{0}_{1}'.format(n_
, pname
)
356 if typ
== 'in' or typ
== 'inout':
358 return template
.format(bitspec
, n_
, ck
, spc
)
361 def mk_cellconn(self
, *args
):
364 def mkfast_peripheral(self
, size
=0):
367 def mkslow_peripheral(self
, size
=0):
370 def mksuffix(self
, name
, i
):
373 def __mk_connection(self
, con
, aname
, count
, fabricname
):
374 txt
= "mkConnection ({2}.v_to_slaves\n" + \
375 " [fromInteger(valueOf({1}))],\n" + \
378 print "PBase __mk_connection", self
.name
, aname
381 con
= con
.format(count
, aname
)
382 return txt
.format(con
, aname
, fabricname
)
384 def __mk_master_connection(self
, con
, aname
, count
, fabricname
):
385 txt
= "mkConnection ({0}, {2}.v_from_masters\n" + \
386 " [fromInteger(valueOf({1}))]);\n"
388 print "PBase __mk_master_connection", self
.name
, aname
391 con
= con
.format(count
, aname
)
392 return txt
.format(con
, aname
, fabricname
)
394 def mk_master_connection(self
, count
, fabricname
, typ
, name
=None):
395 if not self
.has_axi_master():
399 print "PBase mk_master_conn", self
.name
, count
400 aname
= self
.axi_master_name(name
, count
, typ
)
402 connections
= self
._mk
_connection
(name
, count
, True)
403 if not isinstance(connections
, list):
404 connections
= [connections
]
405 for con
in connections
:
406 ret
.append(self
.__mk
_master
_connection
(con
, aname
, count
,
408 return '\n'.join(ret
)
410 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
413 print "PBase mk_conn", self
.name
, count
415 connections
= self
._mk
_connection
(name
, count
)
416 if not isinstance(connections
, list):
417 connections
= [connections
]
418 for (idx
, con
) in enumerate(connections
):
419 if len(connections
) == 1:
423 aname
= self
.axi_slave_name(idx
, name
, count
, typ
)
424 ret
.append(self
.__mk
_connection
(con
, aname
, count
, fabricname
))
425 return '\n'.join(ret
)
427 def _mk_connection(self
, name
=None, count
=0):
430 def pinname_out(self
, pname
):
433 def pinname_in(self
, pname
):
436 def pinname_outen(self
, pname
):
439 def ifname_tweak(self
, pname
, typ
, txt
):
442 def pinname_tweak(self
, pname
, typ
, txt
):
448 def mk_plic(self
, inum
, irq_offs
):
450 print "mk_plic", self
.name
, inum
, irq_offs
451 niq
= self
.num_irqs()
453 return ('', irq_offs
)
454 name
= self
.get_iname(inum
)
455 res
.append("// PLIC rules for {0}".format(name
))
456 for idx
in range(niq
):
457 plic_obj
= self
.plic_object(name
, idx
)
458 print "plic_obj", name
, idx
, plic_obj
459 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
461 irq_offs
+= 1 # increment to next irq
462 return ('\n'.join(res
), irq_offs
)
464 def mk_ext_ifacedef(self
, iname
, inum
):
467 def extfastifinstance(self
, name
, count
):
470 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
474 pname
= self
.get_iname(count
)
478 sname
= self
.peripheral
.iname().format(count
)
479 template
= "interface {0}{3} = {2}{1}{4};"
480 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
482 def extifinstance2(self
, name
, count
):
485 def extifinstance(self
, name
, count
):
486 return self
._extifinstance
(name
, count
, "",
487 "pinmux.peripheral_side.")
491 rule rl_connect_{0}_to_plic_{2};
492 if({1} == 1'b1) begin
493 ff_gateway_queue[{2}].enq(1);
494 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
499 axi_master_declarations
= """\
500 typedef 0 Dmem_master_num;
501 typedef 1 Imem_master_num;
503 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
505 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
507 typedef TAdd#(DMA_master_num,1)
511 axi_fastslave_declarations
= """\
513 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
514 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
516 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
518 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
520 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
522 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
524 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
525 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
527 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
530 axi_slave_declarations
= """\
531 typedef 0 SlowMaster;
533 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
535 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
537 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
539 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
542 pinmux_cellrule
= """\
543 rule connect_select_lines_pinmux;
549 class CallFn(object):
550 def __init__(self
, peripheral
, name
):
551 self
.peripheral
= peripheral
554 def __call__(self
, *args
):
555 #print "__call__", self.name, self.peripheral.slow, args
556 if not self
.peripheral
.slow
:
558 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
561 class PeripheralIface(object):
562 def __init__(self
, ifacename
):
564 slow
= slowfactory
.getcls(ifacename
)
565 print "Iface", ifacename
, slow
567 self
.slow
= slow(ifacename
)
568 self
.slow
.peripheral
= self
569 for fname
in ['slowimport',
571 'extifinstance2', 'extifinstance', 'extifdecl',
572 'slowifdecl', 'slowifdeclmux',
575 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
577 'mk_plic', 'mk_ext_ifacedef',
578 '_mk_clk_con', 'mk_ext_ifacedef',
579 'mk_connection', 'mk_master_connection',
580 'mk_cellconn', '_mk_pincon']:
581 fn
= CallFn(self
, fname
)
582 setattr(self
, fname
, types
.MethodType(fn
, self
))
584 #print "PeripheralIface"
587 def mksuffix(self
, name
, i
):
588 if self
.slow
is None:
590 return self
.slow
.mksuffix(name
, i
)
592 def axi_reg_def(self
, start
, count
):
595 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
597 def axi_master_idx(self
, start
, count
, typ
):
598 if not self
.slow
or not self
.slow
.has_axi_master():
600 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
602 def axi_slave_idx(self
, start
, count
, typ
):
605 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
607 def axi_fastaddr_map(self
, count
):
610 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
612 def axi_addr_map(self
, count
):
615 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
618 class PeripheralInterfaces(object):
620 self
.fastbusmode
= False
622 def slowimport(self
, *args
):
624 for (name
, count
) in self
.ifacecount
:
625 #print "slowimport", name, self.data[name].slowimport
626 ret
.append(self
.data
[name
].slowimport())
627 return '\n'.join(li(list(filter(None, ret
)), 4))
629 def extfastifinstance(self
, *args
):
631 for (name
, count
) in self
.ifacecount
:
632 for i
in range(count
):
633 iname
= self
.data
[name
].iname().format(i
)
634 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
635 if self
.is_on_fastbus(name
, i
):
637 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
638 return '\n'.join(li(list(filter(None, ret
)), 8))
640 def extifinstance2(self
, *args
):
642 for (name
, count
) in self
.ifacecount
:
643 for i
in range(count
):
644 iname
= self
.data
[name
].iname().format(i
)
645 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
646 return '\n'.join(li(list(filter(None, ret
)), 8))
648 def extifinstance(self
, *args
):
650 for (name
, count
) in self
.ifacecount
:
651 for i
in range(count
):
652 iname
= self
.data
[name
].iname().format(i
)
653 if not self
.is_on_fastbus(name
, i
):
655 ret
.append(self
.data
[name
].extifinstance(name
, i
))
656 return '\n'.join(li(list(filter(None, ret
)), 8))
658 def extifdecl(self
, *args
):
660 for (name
, count
) in self
.ifacecount
:
661 for i
in range(count
):
662 if not self
.is_on_fastbus(name
, i
):
664 ret
.append(self
.data
[name
].extifdecl(name
, i
))
665 return '\n'.join(li(list(filter(None, ret
)), 8))
667 def slowifdeclmux(self
, *args
):
669 for (name
, count
) in self
.ifacecount
:
670 for i
in range(count
):
671 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
672 return '\n'.join(li(list(filter(None, ret
)), 8))
674 def fastifdecl(self
, *args
):
676 for (name
, count
) in self
.ifacecount
:
677 for i
in range(count
):
678 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
679 if self
.is_on_fastbus(name
, i
):
681 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
682 return '\n'.join(li(list(filter(None, ret
)), 4))
684 def slowifdecl(self
, *args
):
686 for (name
, count
) in self
.ifacecount
:
687 for i
in range(count
):
688 if self
.is_on_fastbus(name
, i
):
690 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
691 return '\n'.join(list(filter(None, ret
)))
693 def axi_fastmem_def(self
, *args
):
694 return self
._axi
_reg
_def
(0x50000000, *args
)
696 def axi_reg_def(self
, *args
):
697 return self
._axi
_reg
_def
(0x00011100, *args
)
699 def _axi_reg_def(self
, start
, *args
):
701 for (name
, count
) in self
.ifacecount
:
702 for i
in range(count
):
703 if self
.is_on_fastbus(name
, i
):
705 x
= self
.data
[name
].axi_reg_def(start
, i
)
706 #print ("ifc", name, x)
710 return '\n'.join(list(filter(None, ret
)))
712 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
714 for (name
, count
) in self
.ifacecount
:
715 for i
in range(count
):
716 if self
.is_on_fastbus(name
, i
):
719 fn
= self
.data
[name
].axi_master_idx
721 fn
= self
.data
[name
].axi_slave_idx
722 (rdef
, offs
) = fn(start
, i
, idxtype
)
723 #print ("ifc", name, rdef, offs)
726 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
727 decls
= '\n'.join(list(filter(None, ret
)))
728 return template
.format(decls
)
730 def axi_slave_idx(self
, *args
):
731 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
734 def axi_fastslave_idx(self
, *args
):
735 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
738 def axi_master_idx(self
, *args
):
739 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
742 def axi_fastslave_idx(self
, *args
):
743 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
746 def axi_fastaddr_map(self
, *args
):
748 for (name
, count
) in self
.ifacecount
:
749 for i
in range(count
):
750 if self
.is_on_fastbus(name
, i
):
752 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
753 return '\n'.join(li(list(filter(None, ret
)), 8))
755 def axi_addr_map(self
, *args
):
757 for (name
, count
) in self
.ifacecount
:
758 for i
in range(count
):
759 if self
.is_on_fastbus(name
, i
):
761 ret
.append(self
.data
[name
].axi_addr_map(i
))
762 return '\n'.join(li(list(filter(None, ret
)), 8))
764 def mkfast_peripheral(self
, *args
):
766 for (name
, count
) in self
.ifacecount
:
767 for i
in range(count
):
768 if self
.is_on_fastbus(name
, i
):
770 #print "mkfast", name, count
771 x
= self
.data
[name
].mkfast_peripheral()
773 suffix
= self
.data
[name
].mksuffix(name
, i
)
774 ret
.append(x
.format(suffix
))
775 return '\n'.join(li(list(filter(None, ret
)), 8))
777 def mkslow_peripheral(self
, *args
):
779 for (name
, count
) in self
.ifacecount
:
780 for i
in range(count
):
781 if self
.is_on_fastbus(name
, i
):
783 #print "mkslow", name, count
784 x
= self
.data
[name
].mkslow_peripheral()
786 suffix
= self
.data
[name
].mksuffix(name
, i
)
787 ret
.append(x
.format(suffix
))
788 return '\n'.join(li(list(filter(None, ret
)), 8))
790 def _mk_connection(self
, fabric
, typ
, indent
, master
, *args
):
792 for (name
, count
) in self
.ifacecount
:
793 for i
in range(count
):
794 if self
.is_on_fastbus(name
, i
):
797 txt
= self
.data
[name
].mk_master_connection(i
, fabric
, typ
)
799 txt
= self
.data
[name
].mk_connection(i
, fabric
, typ
)
803 return '\n'.join(li(list(filter(None, ret
)), indent
))
805 def mk_master_connection(self
, *args
):
806 return self
._mk
_connection
("fabric", "fast", 8, True, *args
)
808 def mk_fast_connection(self
, *args
):
809 return self
._mk
_connection
("fabric", "fast", 12, False, *args
)
811 def mk_connection(self
, *args
):
812 return self
._mk
_connection
("slow_fabric", "", 8, False, *args
)
814 def mk_cellconn(self
):
817 for (name
, count
) in self
.ifacecount
:
818 for i
in range(count
):
819 if self
.is_on_fastbus(name
, i
):
821 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
824 (txt
, cellcount
) = res
826 ret
= li('\n'.join(list(filter(None, ret
))), 4)
827 return li(pinmux_cellrule
.format(ret
), 4)
830 return self
._mk
_pincon
("slow")
832 def mk_fast_pincon(self
):
833 return self
._mk
_pincon
("fast")
835 def _mk_pincon(self
, typ
):
837 for (name
, count
) in self
.ifacecount
:
838 for i
in range(count
):
839 if self
.is_on_fastbus(name
, i
):
841 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
843 return '\n'.join(li(list(filter(None, ret
)), 4))
845 def mk_dma_irq(self
):
853 for (name
, count
) in self
.ifacecount
:
855 for i
in range(count
):
856 if not self
.is_on_fastbus(name
, i
):
858 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
862 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
863 ifacerules
.append(txt
)
864 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
866 ifacerules
= list(filter(None, ifacerules
))
868 txt
= "rule synchronize_%s_interrupts;" % name
871 rules
.append("endrule")
873 cnct
= list(filter(None, cnct
))
875 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
876 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
879 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
881 cnct
.append(" dma.interrupt_from_peripherals(\n" +
882 " lv_interrupt_to_DMA);")
883 cnct
.append("endrule;")
885 ret
= list(filter(None, sync
+ rules
+ cnct
))
887 return '\n'.join(ret
)
889 def num_dmachannels(self
):
890 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
892 def mk_ext_ifacedef(self
):
894 for (name
, count
) in self
.ifacecount
:
895 for i
in range(count
):
896 if self
.is_on_fastbus(name
, i
):
898 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
900 return '\n'.join(li(list(filter(None, ret
)), 8))
904 irq_offs
= 8 # XXX: DMA scovers 0-7?
905 for (name
, count
) in self
.ifacecount
:
906 for i
in range(count
):
907 if self
.is_on_fastbus(name
, i
):
909 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
912 (txt
, irq_offs
) = res
914 self
.num_slow_irqs
= irq_offs
915 return '\n'.join(li(list(filter(None, ret
)), 4))
917 def mk_sloirqsdef(self
):
918 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
920 def mk_fastclk_con(self
):
921 return self
._mk
_clk
_con
("fast")
923 def mk_slowclk_con(self
):
924 return self
._mk
_clk
_con
("slow")
926 def _mk_clk_con(self
, ctype
):
928 for (name
, count
) in self
.ifacecount
:
929 for i
in range(count
):
930 if self
.is_on_fastbus(name
, i
):
932 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
934 return '\n'.join(li(list(filter(None, ret
)), 8))
936 def is_on_fastbus(self
, name
, i
):
937 #print "fastbus mode", self.fastbusmode, name, i
938 iname
= self
.data
[name
].iname().format(i
)
940 return iname
not in self
.fastbus
941 return iname
in self
.fastbus
944 class PFactory(object):
945 def getcls(self
, name
):
946 from uart
import uart
947 from quart
import quart
948 from sdmmc
import sdmmc
950 from eint
import eint
951 from rs232
import rs232
953 from eint
import eint
954 from jtag
import jtag
955 from spi
import spi
, mspi
956 from qspi
import qspi
, mqspi
957 from gpio
import gpio
958 from rgbttl
import rgbttl
959 from flexbus
import flexbus
960 from sdram
import sdram
962 for k
, v
in {'uart': uart
,
979 if name
.startswith(k
):
984 slowfactory
= PFactory()
986 if __name__
== '__main__':
990 i
= PeripheralIface('uart')
992 i
= PeripheralIface('gpioa')