src/bsv/peripheral_gen/eint.py

   1 from bsv.peripheral_gen.base import PBase
   2
   3
   4 class eint(PBase):
   5
   6     def slowimport(self):
   7         size = len(self.peripheral.pinspecs)
   8         return "`define NUM_EINTS %d" % size
   9
  10     def mkslow_peripheral(self, size=0):
  11         size = len(self.peripheral.pinspecs)
  12         return "Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
  13
  14     def axi_slave_name(self, name, ifacenum, typ=''):
  15         return ''
  16
  17     def axi_slave_idx(self, idx, name, ifacenum, typ):
  18         return ('', 0)
  19
  20     def axi_addr_map(self, name, ifacenum):
  21         return ''
  22
  23     def ifname_tweak(self, pname, typ, txt):
  24         if typ != 'in':
  25             return txt
  26         print "ifnameweak", pname, typ, txt
  27         return "wr_interrupt[{0}] <= ".format(pname)
  28
  29     def _mk_pincon(self, name, count, typ):
  30         assert typ == 'slow', 'TODO: mkConnection for fast'
  31         ret = [PBase._mk_pincon(self, name, count, typ)]
  32         size = len(self.peripheral.pinspecs)
  33         ret.append(eint_pincon_template.format(size))
  34         ret.append("rule con_%s%d_io_in;" % (name, count))
  35         ret.append("     wr_interrupt <= ({")
  36         for idx, p in enumerate(self.peripheral.pinspecs):
  37             pname = p['name']
  38             sname = self.peripheral.pname(pname).format(count)
  39             ps = "pinmux.peripheral_side.eint.%s" % sname
  40             comma = '' if idx == size - 1 else ','
  41             ret.append("             {0}{1}".format(ps, comma))
  42         ret.append("     });")
  43         ret.append("endrule")
  44
  45         return '\n'.join(ret)
  46
  47
  48 eint_pincon_template = '''\
  49     // EINT is offset at end of other peripheral interrupts
  50 `ifdef PLIC
  51     for(Integer i=0;i<{0};i=i+ 1)begin
  52       rule connect_int_to_plic(wr_interrupt[i]==1);
  53                 ff_gateway_queue[i+`NUM_SLOW_IRQS].enq(1);
  54                 plic.ifc_external_irq[i+`NUM_SLOW_IRQS].irq_frm_gateway(True);
  55       endrule
  56     end
  57 `endif
  58 '''