src/bsv/peripheral_gen/eint.py

   1 from bsv.peripheral_gen.base import PBase
   2
   3
   4 class eint(PBase):
   5
   6     def slowimport(self):
   7         size = len(self.peripheral.pinspecs)
   8         return "    `define NUM_EINTS %d" % size
   9
  10     def mkslow_peripheral(self, size=0):
  11         size = len(self.peripheral.pinspecs)
  12         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
  13
  14     def axi_slave_name(self, name, ifacenum):
  15         return ''
  16
  17     def axi_slave_idx(self, idx, name, ifacenum, typ):
  18         return ('', 0)
  19
  20     def axi_addr_map(self, name, ifacenum):
  21         return ''
  22
  23     def ifname_tweak(self, pname, typ, txt):
  24         if typ != 'in':
  25             return txt
  26         print "ifnameweak", pname, typ, txt
  27         return "wr_interrupt[{0}] <= ".format(pname)
  28
  29     def mk_pincon(self, name, count):
  30         ret = [PBase.mk_pincon(self, name, count)]
  31         size = len(self.peripheral.pinspecs)
  32         ret.append(eint_pincon_template.format(size))
  33         ret.append("    rule con_%s%d_io_in;" % (name, count))
  34         ret.append("    wr_interrupt <= ({")
  35         for idx, p in enumerate(self.peripheral.pinspecs):
  36             pname = p['name']
  37             sname = self.peripheral.pname(pname).format(count)
  38             ps = "pinmux.peripheral_side.eint.%s" % sname
  39             comma = '' if idx == size - 1 else ','
  40             ret.append("             {0}{1}".format(ps, comma))
  41         ret.append("        });")
  42         ret.append("    endrule")
  43
  44         return '\n'.join(ret)
  45
  46
  47 eint_pincon_template = '''\
  48     // EINT is offset at end of other peripheral interrupts
  49 `ifdef PLIC
  50     for(Integer i=0;i<{0};i=i+ 1)begin
  51       rule connect_int_to_plic(wr_interrupt[i]==1);
  52                 ff_gateway_queue[i+`NUM_SLOW_IRQS].enq(1);
  53                 plic.ifc_external_irq[i+`NUM_SLOW_IRQS].irq_frm_gateway(True);
  54       endrule
  55     end
  56 `endif
  57 '''