add fast bus instance
[pinmux.git] / src / bsv / peripheral_gen / jtag.py
1 from bsv.peripheral_gen.base import PBase
2
3
4 class jtag(PBase):
5
6 def slowimport(self):
7 return " import jtagtdm::*;\n"
8
9 def extfastifinstance(self, name, count):
10 # YUK!
11 print "jtag", name, count
12 return """\
13 method Action tms_i(Bit#(1) tms);
14 {0}.tms_i(tms);
15 endmethod
16 method Action tdi_i(Bit#(1) tdi);
17 {0}.tdi_i(tdi);
18 endmethod
19 method Action bs_chain_i(Bit#(1) bs_chain);
20 {0}.bs_chain_i(bs_chain);
21 endmethod
22 method Bit#(1) shiftBscan2Edge={0}.shiftBscan2Edge;
23 method Bit#(1) selectJtagInput={0}.selectJtagInput;
24 method Bit#(1) selectJtagOutput={0}.selectJtagOutput;
25 method Bit#(1) updateBscan={0}.updateBscan;
26 method Bit#(1) bscan_in={0}.bscan_in;
27 method Bit#(1) scan_shift_en={0}.scan_shift_en;
28 method Bit#(1) tdo={0}.tdo;
29 method Bit#(1) tdo_oe={0}.tdo_oe;
30 """.format(self.name, count)
31
32
33
34 def fastifdecl(self, name, count):
35 # YUK!
36 template = """ \
37 (*always_ready,always_enabled*) method Action tms_i(Bit#(1) tms);
38 (*always_ready,always_enabled*) method Action tdi_i(Bit#(1) tdi);
39 (*always_ready,always_enabled*)
40 method Action bs_chain_i(Bit#(1) bs_chain);
41 (*always_ready,always_enabled*) method Bit#(1) shiftBscan2Edge;
42 (*always_ready,always_enabled*) method Bit#(1) selectJtagInput;
43 (*always_ready,always_enabled*) method Bit#(1) selectJtagOutput;
44 (*always_ready,always_enabled*) method Bit#(1) updateBscan;
45 (*always_ready,always_enabled*) method Bit#(1) bscan_in;
46 (*always_ready,always_enabled*) method Bit#(1) scan_shift_en;
47 (*always_ready,always_enabled*) method Bit#(1) tdo;
48 (*always_ready,always_enabled*) method Bit#(1) tdo_oe;
49 """
50 return template
51
52 def mkfast_peripheral(self):
53 return """\
54 Ifc_jtagdtm jtag{0} <-mkjtagdtm(clocked_by tck, reset_by trst);
55 rule drive_tmp_scan_outs;
56 jtag{0}.scan_out_1_i(1'b0);
57 jtag{0}.scan_out_2_i(1'b0);
58 jtag{0}.scan_out_3_i(1'b0);
59 jtag{0}.scan_out_4_i(1'b0);
60 jtag{0}.scan_out_5_i(1'b0);
61 endrule
62 """
63 def axi_slave_name(self, name, ifacenum, typ=''):
64 return ''
65
66 def axi_slave_idx(self, idx, name, ifacenum, typ):
67 return ('', 0)
68
69 def axi_addr_map(self, name, ifacenum):
70 return ''