76d5481f07540eefa892617671c4096d9d6944b8
1 from bsv
.peripheral_gen
.base
import PBase
7 return "import sdr_top::*;"
9 def num_axi_regs32(self
):
10 return 0x400000 # defines an entire memory range
12 def extfastifinstance(self
, name
, count
):
13 return "// TODO" + self
._extifinstance
(name
, count
, "_out", "", True,
16 def fastifdecl(self
, name
, count
):
17 return "// (*always_ready*) interface " + \
18 "Ifc_sdram_out sdr{0}_out;".format(count
)
20 def get_clock_reset(self
, name
, count
):
21 return "slow_clock, slow_reset"
23 def mkfast_peripheral(self
):
24 return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
26 def _mk_connection(self
, name
=None, count
=0):
27 return ["sdr{0}.axi4_slave_sdram",
28 "sdr{0}.axi4_slave_cntrl_reg"]
31 def pinname_in(self
, pname
):
32 return {'ta': 'sdram_side.m_tAn',
35 def pinname_out(self
, pname
):
36 return {'ale': 'sdram_side.m_ALE',
37 'oe': 'sdram_side.m_OEn',
38 'tbst': 'sdram_side.m_TBSTn',
39 'rw': 'sdram_side.m_R_Wn',
42 def _mk_clk_con(self
, name
, count
, ctype
):
43 ret
= [PBase
._mk
_clk
_con
(self
, name
, count
, ctype
)]
44 for pname
, sz
, ptype
in [
48 ('ad_out', 32, 'out'),
50 ('ad_out_en', 32, 'out'),
52 bitspec
= "Bit#(%d)" % sz
53 txt
= self
._mk
_clk
_vcon
(name
, count
, ctype
, ptype
, pname
, bitspec
)
57 def _mk_pincon(self
, name
, count
, typ
):
58 ret
= [PBase
._mk
_pincon
(self
, name
, count
, typ
)]
59 assert typ
== 'fast' # TODO slow?
60 for pname
, stype
, ptype
in [
61 ('cs', 'm_FBCSn', 'out'),
62 ('bwe', 'm_BWEn', 'out'),
63 ('tsiz', 'm_TSIZ', 'out'),
64 ('ad_out', 'm_AD', 'out'),
65 ('ad_in', 'm_din', 'in'),
66 ('ad_out_en', 'm_OE32n', 'out'),
68 ret
.append(self
._mk
_vpincon
(name
, count
, typ
, ptype
, pname
,
69 "sdram_side.{0}".format(stype
)))