src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 '''
  43 footer = '''
  44    endmodule
  45 endpackage
  46 '''
  47
  48
  49 def pinmuxgen(pth=None, verify=True):
  50     """ populating the file with the code
  51     """
  52
  53     p = Parse(pth, verify)
  54     iocells = Interfaces()
  55     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  56     ifaces = Interfaces(pth)
  57     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  58     init(p, ifaces)
  59
  60     bp = 'bsv_src'
  61     if pth:
  62         bp = os.path.join(pth, bp)
  63     if not os.path.exists(bp):
  64         os.makedirs(bp)
  65     bl = os.path.join(bp, 'bsv_lib')
  66     if not os.path.exists(bl):
  67         os.makedirs(bl)
  68
  69     cwd = os.path.split(__file__)[0]
  70
  71     # copy over template and library files
  72     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  73                     os.path.join(bp, 'Makefile'))
  74     cwd = os.path.join(cwd, 'bsv_lib')
  75     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
  76                   'gpio.bsv', 'mux.bsv',
  77                   'AXI4_Types.bsv', 'defined_types.bsv',
  78                   'AXI4_Fabric.bsv', 'Uart16550.bsv',
  79                   'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
  80                   'Uart_bs.bsv', 'RS232_modified.bsv',
  81                   'AXI4Lite_AXI4_Bridge.bsv',
  82                   'I2C_top.bsv', 'I2C_Defs.bsv',
  83                   'plic.bsv', 'Cur_Cycle.bsv',
  84                   'ClockDiv.bsv', 'axi_addr_generator.bsv',
  85                   'pwm.bsv', 'qspi.bsv', 'qspi.defs',
  86                   ]:
  87         shutil.copyfile(os.path.join(cwd, fname),
  88                         os.path.join(bl, fname))
  89
  90     bus = os.path.join(bp, 'busenable.bsv')
  91     pmp = os.path.join(bp, 'pinmux.bsv')
  92     ptp = os.path.join(bp, 'PinTop.bsv')
  93     bvp = os.path.join(bp, 'bus.bsv')
  94     idef = os.path.join(bp, 'instance_defines.bsv')
  95     slow = os.path.join(bp, 'slow_peripherals.bsv')
  96     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  97
  98     write_pmp(pmp, p, ifaces, iocells)
  99     write_ptp(ptp, p, ifaces)
 100     write_bvp(bvp, p, ifaces)
 101     write_bus(bus, p, ifaces)
 102     write_instances(idef, p, ifaces)
 103     write_slow(slow, slowt, p, ifaces, iocells)
 104
 105
 106 def write_slow(slow, template, p, ifaces, iocells):
 107     """ write out the slow_peripherals.bsv file.
 108         joins all the peripherals together into one AXI Lite interface
 109     """
 110     with open(template) as bsv_file:
 111         template = bsv_file.read()
 112     imports = ifaces.slowimport()
 113     ifdecl = ifaces.slowifdecl()
 114     regdef = ifaces.axi_reg_def()
 115     slavedecl = ifaces.axi_slave_idx()
 116     fnaddrmap = ifaces.axi_addr_map()
 117     mkslow = ifaces.mkslow_peripheral()
 118     mkcon = ifaces.mk_connection()
 119     mkcellcon = ifaces.mk_cellconn()
 120     pincon = ifaces.mk_pincon()
 121     with open(slow, "w") as bsv_file:
 122         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
 123                                        fnaddrmap, mkslow, mkcon, mkcellcon,
 124                                        pincon))
 125
 126
 127 def write_bus(bus, p, ifaces):
 128     # package and interface declaration followed by
 129     # the generic io_cell definition
 130     with open(bus, "w") as bsv_file:
 131         ifaces.busfmt(bsv_file)
 132
 133
 134 def write_pmp(pmp, p, ifaces, iocells):
 135     # package and interface declaration followed by
 136     # the generic io_cell definition
 137     with open(pmp, "w") as bsv_file:
 138         bsv_file.write(header)
 139
 140         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 141         bsv_file.write('''\
 142    interface MuxSelectionLines;
 143
 144       // declare the method which will capture the user pin-mux
 145       // selection values.The width of the input is dependent on the number
 146       // of muxes happening per IO. For now we have a generalized width
 147       // where each IO will have the same number of muxes.''')
 148
 149         for cell in p.muxed_cells:
 150             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 151
 152         bsv_file.write("\n      endinterface\n")
 153
 154         bsv_file.write('''
 155
 156       interface IOCellSide;
 157       // declare the interface to the IO cells.
 158       // Each IO cell will have 1 input field (output from pin mux)
 159       // and an output and out-enable field (input to pinmux)''')
 160
 161         # == create method definitions for all iocell interfaces ==#
 162         iocells.ifacefmt(bsv_file)
 163
 164         # ===== finish interface definition and start module definition=======
 165         bsv_file.write("\n      endinterface\n")
 166
 167         # ===== io cell definition =======
 168         bsv_file.write('''
 169
 170       interface PeripheralSide;
 171       // declare the interface to the peripherals
 172       // Each peripheral's function will be either an input, output
 173       // or be bi-directional.  an input field will be an output from the
 174       // peripheral and an output field will be an input to the peripheral.
 175       // Bi-directional functions also have an output-enable (which
 176       // again comes *in* from the peripheral)''')
 177         # ==============================================================
 178
 179         # == create method definitions for all peripheral interfaces ==#
 180         ifaces.ifacefmt(bsv_file)
 181         bsv_file.write("\n      endinterface\n")
 182
 183         # ===== finish interface definition and start module definition=======
 184         bsv_file.write('''
 185
 186    interface Ifc_pinmux;
 187       // this interface controls how each IO cell is routed.  setting
 188       // any given IO cell's mux control value will result in redirection
 189       // of not just the input or output to different peripheral functions
 190       // but also the *direction* control - if appropriate - as well.
 191       interface MuxSelectionLines mux_lines;
 192
 193       // this interface contains the inputs, outputs and direction-control
 194       // lines for all peripherals.  GPIO is considered to also be just
 195       // a peripheral because it also has in, out and direction-control.
 196       interface PeripheralSide peripheral_side;
 197
 198       // this interface is to be linked to the individual IO cells.
 199       // if looking at a "non-muxed" GPIO design, basically the
 200       // IO cell input, output and direction-control wires are cut
 201       // (giving six pairs of dangling wires, named left and right)
 202       // these iocells are routed in their place on one side ("left")
 203       // and the matching *GPIO* peripheral interfaces in/out/dir
 204       // connect to the OTHER side ("right").  the result is that
 205       // the muxer settings end up controlling the routing of where
 206       // the I/O from the IOcell actually goes.
 207       interface IOCellSide iocell_side;
 208    endinterface
 209    (*synthesize*)
 210    module mkpinmux(Ifc_pinmux);
 211 ''')
 212         # ====================================================================
 213
 214         # ======================= create wire and registers =================#
 215         bsv_file.write('''
 216       // the followins wires capture the pin-mux selection
 217       // values for each mux assigned to a CELL
 218 ''')
 219         for cell in p.muxed_cells:
 220             bsv_file.write(mux_interface.wirefmt(
 221                 cell[0], cell_bit_width))
 222
 223         iocells.wirefmt(bsv_file)
 224         ifaces.wirefmt(bsv_file)
 225
 226         bsv_file.write("\n")
 227         # ====================================================================
 228         # ========================= Actual pinmuxing ========================#
 229         bsv_file.write('''
 230       /*====== This where the muxing starts for each io-cell======*/
 231       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 232 ''')
 233         bsv_file.write(p.pinmux)
 234         bsv_file.write('''
 235       /*============================================================*/
 236 ''')
 237         # ====================================================================
 238         # ================= interface definitions for each method =============#
 239         bsv_file.write('''
 240     interface mux_lines = interface MuxSelectionLines
 241 ''')
 242         for cell in p.muxed_cells:
 243             bsv_file.write(
 244                 mux_interface.ifacedef(
 245                     cell[0], cell_bit_width))
 246         bsv_file.write("\n    endinterface;")
 247
 248         bsv_file.write('''
 249     interface iocell_side = interface IOCellSide
 250 ''')
 251         iocells.ifacedef(bsv_file)
 252         bsv_file.write("\n     endinterface;")
 253
 254         bsv_file.write('''
 255     interface peripheral_side = interface PeripheralSide
 256 ''')
 257         ifaces.ifacedef(bsv_file)
 258         bsv_file.write("\n     endinterface;")
 259
 260         bsv_file.write(footer)
 261         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 262         # ======================================================================
 263
 264
 265 def write_ptp(ptp, p, ifaces):
 266     with open(ptp, 'w') as bsv_file:
 267         bsv_file.write(copyright + '''
 268 package PinTop;
 269     import pinmux::*;
 270     interface Ifc_PintTop;
 271         method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
 272         method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
 273         interface PeripheralSide peripheral_side;
 274     endinterface
 275
 276     module mkPinTop(Ifc_PintTop);
 277         // instantiate the pin-mux module here
 278         Ifc_pinmux pinmux <-mkpinmux;
 279
 280         // declare the registers which will be used to mux the IOs
 281 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
 282
 283         cell_bit_width = str(p.cell_bitwidth)
 284         for cell in p.muxed_cells:
 285             bsv_file.write('''
 286                 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
 287                 cell_bit_width, cell[0]))
 288
 289         bsv_file.write('''
 290         // rule to connect the registers to the selection lines of the
 291         // pin-mux module
 292         rule connect_selection_registers;''')
 293
 294         for cell in p.muxed_cells:
 295             bsv_file.write('''
 296           pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
 297
 298         bsv_file.write('''
 299         endrule
 300         // method definitions for the write user interface
 301         method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
 302           Bool err=False;
 303           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 304                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 305         index = 0
 306         for cell in p.muxed_cells:
 307             bsv_file.write('''
 308             {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
 309             index = index + 1
 310
 311         bsv_file.write('''
 312             default: err=True;
 313           endcase
 314           return err;
 315         endmethod''')
 316
 317         bsv_file.write('''
 318         // method definitions for the read user interface
 319         method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
 320           Bool err=False;
 321           Bit#(32) data=0;
 322           case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
 323                                          p.ADDR_WIDTH, p.DATA_WIDTH))
 324         index = 0
 325         for cell in p.muxed_cells:
 326             bsv_file.write('''
 327                 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
 328             index = index + 1
 329
 330         bsv_file.write('''
 331             default:err=True;
 332           endcase
 333           return tuple2(err,data);
 334         endmethod
 335         interface peripheral_side=pinmux.peripheral_side;
 336     endmodule
 337 endpackage
 338 ''')
 339
 340
 341 def write_bvp(bvp, p, ifaces):
 342     # ######## Generate bus transactors ################
 343     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 344               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 345     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 346         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 347
 348     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 349     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 350     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 351               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 352     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 353         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 354     with open(bvp, 'w') as bsv_file:
 355         # assume here that all muxes have a 1:1 gpio
 356         cfg = []
 357         decl = []
 358         idec = []
 359         iks = sorted(ifaces.keys())
 360         for iname in iks:
 361             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 362                 continue
 363             bank = iname[4:]
 364             ifc = ifaces[iname]
 365             npins = len(ifc.pinspecs)
 366             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 367                                       0,  # USERSPACE
 368                                       bank, npins))
 369             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 370                                      0,  # USERSPACE
 371                                      bank, npins))
 372             decl.append(gpiodec.format(npins, bank))
 373             decl.append(muxdec .format(npins, bank))
 374             idec.append(gpioifc.format(bank))
 375             idec.append(muxifc.format(bank))
 376         print dir(ifaces)
 377         print ifaces.items()
 378         print dir(ifaces['gpioa'])
 379         print ifaces['gpioa'].pinspecs
 380         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 381         gpiocfg = '\n'.join(cfg)
 382         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 383     # ##################################################
 384
 385
 386 def write_instances(idef, p, ifaces):
 387     with open(idef, 'w') as bsv_file:
 388         txt = '''\
 389 `define ADDR {0}
 390 `define PADDR {0}
 391 `define DATA {1}
 392 `define Reg_width {1}
 393 `define USERSPACE 0
 394
 395 // TODO: work out if these are needed
 396 `define PWM_AXI4Lite
 397 `define PRFDEPTH 6
 398 `define VADDR 39
 399 `define DCACHE_BLOCK_SIZE 4
 400 `define DCACHE_WORD_SIZE 8
 401 `define PERFMONITORS                            64
 402 `define DCACHE_WAYS 4
 403 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 404 `define PLIC
 405         `define PLICBase                'h0c000000
 406         `define PLICEnd         'h10000000
 407 `define INTERRUPT_PINS 64
 408
 409 `define BAUD_RATE 130
 410 `ifdef simulate
 411   `define BAUD_RATE 5 //130 //
 412 `endif
 413 '''
 414         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))