src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     cwd = os.path.join(cwd, 'bsv_lib')
  78     for fname in []:
  79         shutil.copyfile(os.path.join(cwd, fname),
  80                         os.path.join(bl, fname))
  81
  82     bus = os.path.join(bp, 'busenable.bsv')
  83     pmp = os.path.join(bp, 'pinmux.bsv')
  84     bvp = os.path.join(bp, 'bus.bsv')
  85     idef = os.path.join(bp, 'instance_defines.bsv')
  86     slow = os.path.join(bp, 'slow_peripherals.bsv')
  87     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  88     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  89     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  90     fastmf = os.path.join(bp, 'fast_memory_map.bsv')
  91     fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
  92     soc = os.path.join(bp, 'socgen.bsv')
  93     soct = os.path.join(cwd, 'soc_template.bsv')
  94
  95     write_pmp(pmp, p, ifaces, iocells)
  96     write_bvp(bvp, p, ifaces)
  97     write_bus(bus, p, ifaces)
  98     write_instances(idef, p, ifaces)
  99     write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
 100     write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
 101
 102
 103 def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
 104     """ write out the slow_peripherals.bsv file.
 105         joins all the peripherals together into one AXI Lite interface
 106     """
 107     imports = ifaces.slowimport()
 108     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 109     regdef = ifaces.axi_reg_def()
 110     slavedecl = ifaces.axi_slave_idx()
 111     fnaddrmap = ifaces.axi_addr_map()
 112     mkslow = ifaces.mkslow_peripheral()
 113     mkcon = ifaces.mk_connection()
 114     mkcellcon = ifaces.mk_cellconn()
 115     pincon = ifaces.mk_pincon()
 116     inst = ifaces.extifinstance()
 117     inst2 = ifaces.extifinstance2()
 118     mkplic = ifaces.mk_plic()
 119     numsloirqs = ifaces.mk_sloirqsdef()
 120     ifacedef = ifaces.mk_ext_ifacedef()
 121     ifacedef = ifaces.mk_ext_ifacedef()
 122     clockcon = ifaces.mk_slowclk_con()
 123
 124     with open(slow, "w") as bsv_file:
 125         with open(slowt) as f:
 126             slowt = f.read()
 127         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 128                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 129                                     pincon, inst, mkplic,
 130                                     numsloirqs, ifacedef,
 131                                     inst2, clockcon))
 132
 133     with open(slowmf, "w") as bsv_file:
 134         with open(slowmt) as f:
 135             slowmt = f.read()
 136         bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
 137
 138
 139 def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
 140     """ write out the soc.bsv file.
 141         joins all the peripherals together as AXI Masters
 142     """
 143     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 144
 145     imports = ifaces.slowimport()
 146     ifdecl = ifaces.fastifdecl()
 147     regdef = ifaces.axi_fastmem_def()
 148     slavedecl = ifaces.axi_fastslave_idx()
 149     mastdecl = ifaces.axi_master_idx()
 150     fnaddrmap = ifaces.axi_fastaddr_map()
 151     mkfast = ifaces.mkfast_peripheral()
 152     mkcon = ifaces.mk_fast_connection()
 153     mkmstcon = ifaces.mk_master_connection()
 154     mkcellcon = ifaces.mk_cellconn()
 155     pincon = ifaces.mk_fast_pincon()
 156     inst = ifaces.extfastifinstance()
 157     mkplic = ifaces.mk_plic()
 158     numsloirqs = ifaces.mk_sloirqsdef()
 159     ifacedef = ifaces.mk_ext_ifacedef()
 160     dma = ifaces.mk_dma_irq()
 161     num_dmachannels = ifaces.num_dmachannels()
 162     clockcon = ifaces.mk_fastclk_con()
 163
 164     with open(soc, "w") as bsv_file:
 165         with open(soct) as f:
 166             soct = f.read()
 167         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 168                                    slavedecl, mastdecl, mkcon,
 169                                    inst, dma, num_dmachannels,
 170                                    pincon, regdef, fnaddrmap,
 171                                    clockcon, mkmstcon,
 172                                    ))
 173
 174     with open(fastmf, "w") as bsv_file:
 175         with open(fastmt) as f:
 176             fastmt = f.read()
 177         bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap))
 178
 179
 180 def write_bus(bus, p, ifaces):
 181     # package and interface declaration followed by
 182     # the generic io_cell definition
 183     with open(bus, "w") as bsv_file:
 184         ifaces.busfmt(bsv_file)
 185
 186
 187 def write_pmp(pmp, p, ifaces, iocells):
 188     # package and interface declaration followed by
 189     # the generic io_cell definition
 190     with open(pmp, "w") as bsv_file:
 191         bsv_file.write(header)
 192
 193         cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
 194         bsv_file.write('''\
 195       (*always_ready,always_enabled*)
 196       interface MuxSelectionLines;
 197
 198       // declare the method which will capture the user pin-mux
 199       // selection values.The width of the input is dependent on the number
 200       // of muxes happening per IO. For now we have a generalized width
 201       // where each IO will have the same number of muxes.''')
 202
 203         for cell in p.muxed_cells:
 204             bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
 205
 206         bsv_file.write("\n      endinterface\n")
 207
 208         bsv_file.write('''
 209
 210       interface IOCellSide;
 211       // declare the interface to the IO cells.
 212       // Each IO cell will have 1 input field (output from pin mux)
 213       // and an output and out-enable field (input to pinmux)''')
 214
 215         # == create method definitions for all iocell interfaces ==#
 216         iocells.ifacefmt(bsv_file)
 217
 218         # ===== finish interface definition and start module definition=======
 219         bsv_file.write("\n      endinterface\n")
 220
 221         ifaces.ifacepfmt(bsv_file)
 222         # ===== io cell definition =======
 223         bsv_file.write('''
 224       (*always_ready,always_enabled*)
 225       interface PeripheralSide;
 226       // declare the interface to the peripherals
 227       // Each peripheral's function will be either an input, output
 228       // or be bi-directional.  an input field will be an output from the
 229       // peripheral and an output field will be an input to the peripheral.
 230       // Bi-directional functions also have an output-enable (which
 231       // again comes *in* from the peripheral)''')
 232         # ==============================================================
 233
 234         # == create method definitions for all peripheral interfaces ==#
 235         ifaces.ifacefmt2(bsv_file)
 236         bsv_file.write("\n      endinterface\n")
 237
 238         # ===== finish interface definition and start module definition=======
 239         bsv_file.write('''
 240
 241    interface Ifc_pinmux;
 242       // this interface controls how each IO cell is routed.  setting
 243       // any given IO cell's mux control value will result in redirection
 244       // of not just the input or output to different peripheral functions
 245       // but also the *direction* control - if appropriate - as well.
 246       interface MuxSelectionLines mux_lines;
 247
 248       // this interface contains the inputs, outputs and direction-control
 249       // lines for all peripherals.  GPIO is considered to also be just
 250       // a peripheral because it also has in, out and direction-control.
 251       interface PeripheralSide peripheral_side;
 252
 253       // this interface is to be linked to the individual IO cells.
 254       // if looking at a "non-muxed" GPIO design, basically the
 255       // IO cell input, output and direction-control wires are cut
 256       // (giving six pairs of dangling wires, named left and right)
 257       // these iocells are routed in their place on one side ("left")
 258       // and the matching *GPIO* peripheral interfaces in/out/dir
 259       // connect to the OTHER side ("right").  the result is that
 260       // the muxer settings end up controlling the routing of where
 261       // the I/O from the IOcell actually goes.
 262       interface IOCellSide iocell_side;
 263    endinterface
 264
 265    (*synthesize*)
 266    module mkpinmux(Ifc_pinmux);
 267 ''')
 268         # ====================================================================
 269
 270         # ======================= create wire and registers =================#
 271         bsv_file.write('''
 272       // the followins wires capture the pin-mux selection
 273       // values for each mux assigned to a CELL
 274 ''')
 275         for cell in p.muxed_cells:
 276             bsv_file.write(mux_interface.wirefmt(
 277                 cell[0], cell_bit_width))
 278
 279         iocells.wirefmt(bsv_file)
 280         ifaces.wirefmt(bsv_file)
 281
 282         bsv_file.write("\n")
 283         # ====================================================================
 284         # ========================= Actual pinmuxing ========================#
 285         bsv_file.write('''
 286       /*====== This where the muxing starts for each io-cell======*/
 287       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 288 ''')
 289         bsv_file.write(p.pinmux)
 290         bsv_file.write('''
 291       /*============================================================*/
 292 ''')
 293         # ====================================================================
 294         # ================= interface definitions for each method =============#
 295         bsv_file.write('''
 296     interface mux_lines = interface MuxSelectionLines
 297 ''')
 298         for cell in p.muxed_cells:
 299             bsv_file.write(
 300                 mux_interface.ifacedef(
 301                     cell[0], cell_bit_width))
 302         bsv_file.write("\n    endinterface;")
 303
 304         bsv_file.write('''
 305
 306     interface iocell_side = interface IOCellSide
 307 ''')
 308         iocells.ifacedef(bsv_file)
 309         bsv_file.write("\n     endinterface;")
 310
 311         bsv_file.write('''
 312
 313      interface peripheral_side = interface PeripheralSide
 314 ''')
 315         ifaces.ifacedef2(bsv_file)
 316         bsv_file.write("\n      endinterface;")
 317
 318         bsv_file.write(footer)
 319         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 320         # ======================================================================
 321
 322
 323 def write_bvp(bvp, p, ifaces):
 324     # ######## Generate bus transactors ################
 325     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 326               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 327     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 328         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 329
 330     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 331     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 332     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 333               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 334     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 335         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 336     with open(bvp, 'w') as bsv_file:
 337         # assume here that all muxes have a 1:1 gpio
 338         cfg = []
 339         decl = []
 340         idec = []
 341         iks = sorted(ifaces.keys())
 342         for iname in iks:
 343             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 344                 continue
 345             bank = iname[4:]
 346             ifc = ifaces[iname]
 347             npins = len(ifc.pinspecs)
 348             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 349                                       0,  # USERSPACE
 350                                       bank, npins))
 351             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 352                                      0,  # USERSPACE
 353                                      bank, npins))
 354             decl.append(gpiodec.format(npins, bank))
 355             decl.append(muxdec .format(npins, bank))
 356             idec.append(gpioifc.format(bank))
 357             idec.append(muxifc.format(bank))
 358         print dir(ifaces)
 359         print ifaces.items()
 360         print dir(ifaces['gpioa'])
 361         print ifaces['gpioa'].pinspecs
 362         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 363         gpiocfg = '\n'.join(cfg)
 364         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 365     # ##################################################
 366
 367
 368 def write_instances(idef, p, ifaces):
 369     with open(idef, 'w') as bsv_file:
 370         txt = '''\
 371 `define ADDR {0}
 372 `define PADDR {2}
 373 `define DATA {1}
 374 `define Reg_width {1}
 375 `define USERSPACE 0
 376 `define RV64
 377
 378 // TODO: work out if these are needed
 379 `define PWM_AXI4Lite
 380 `define PRFDEPTH 6
 381 `define VADDR 39
 382 `define DCACHE_BLOCK_SIZE 4
 383 `define DCACHE_WORD_SIZE 8
 384 `define PERFMONITORS                            64
 385 `define DCACHE_WAYS 4
 386 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 387
 388 // CLINT
 389     `define ClintBase       'h02000000
 390     `define ClintEnd        'h020BFFFF
 391
 392 `define PLIC
 393         `define PLICBase                'h0c000000
 394         `define PLICEnd         'h10000000
 395 `define INTERRUPT_PINS 64
 396
 397 `define BAUD_RATE 130
 398 `ifdef simulate
 399   `define BAUD_RATE 5 //130 //
 400 `endif
 401 '''
 402         bsv_file.write(txt.format(p.ADDR_WIDTH,
 403                                   p.DATA_WIDTH,
 404                                   p.PADDR_WIDTH))