src/bsv/pinmux_generator.py

   1 # ================================== Steps to add peripherals ============
   2 # Step-1:   create interface declaration for the peripheral to be added.
   3 #           Remember these are interfaces defined for the pinmux and hence
   4 #           will be opposite to those defined at the peripheral.
   5 #           For eg. the output TX from the UART will be input (method Action)
   6 #           for the pinmux.
   7 #           These changes will have to be done in interface_decl.py
   8 # Step-2    define the wires that will be required to transfer data from the
   9 #           peripheral interface to the IO cell and vice-versa. Create a
  10 #           mkDWire for each input/output between the peripheral and the
  11 #           pinmux. Also create an implicit wire of GenericIOType for each cell
  12 #           that can be connected to a each bit from the peripheral.
  13 #           These changes will have to be done in wire_def.py
  14 # Step-3:   create the definitions for each of the methods defined above.
  15 #           These changes will have to be done in interface_decl.py
  16 # ========================================================================
  17
  18 # default module imports
  19 import shutil
  20 import os
  21 import os.path
  22 import time
  23
  24 # project module imports
  25 from bsv.interface_decl import Interfaces, mux_interface, io_interface
  26 from parse import Parse
  27 from bsv.actual_pinmux import init
  28 from bsv.bus_transactors import axi4_lite
  29
  30 copyright = '''
  31 /*
  32    This BSV file has been generated by the PinMux tool available at:
  33    https://bitbucket.org/casl/pinmux.
  34
  35    Authors: Neel Gala, Luke
  36    Date of generation: ''' + time.strftime("%c") + '''
  37 */
  38 '''
  39 header = copyright + '''
  40 package pinmux;
  41
  42 import GetPut::*;
  43 import Vector::*;
  44
  45 '''
  46 footer = '''
  47    endmodule
  48 endpackage
  49 '''
  50
  51
  52 def pinmuxgen(pth=None, verify=True):
  53     """ populating the file with the code
  54     """
  55
  56     p = Parse(pth, verify)
  57     iocells = Interfaces()
  58     iocells.ifaceadd('io', p.N_IO, io_interface, 0)
  59     ifaces = Interfaces(pth)
  60     #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
  61     init(p, ifaces)
  62
  63     bp = 'bsv_src'
  64     if pth:
  65         bp = os.path.join(pth, bp)
  66     if not os.path.exists(bp):
  67         os.makedirs(bp)
  68     bl = os.path.join(bp, 'bsv_lib')
  69     if not os.path.exists(bl):
  70         os.makedirs(bl)
  71
  72     cwd = os.path.split(__file__)[0]
  73
  74     # copy over template and library files
  75     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
  76                     os.path.join(bp, 'Makefile'))
  77     shutil.copyfile(os.path.join(cwd, 'Makefile.peripherals.template'),
  78                     os.path.join(bp, 'Makefile.peripherals'))
  79     cwd = os.path.join(cwd, 'bsv_lib')
  80     for fname in []:
  81         shutil.copyfile(os.path.join(cwd, fname),
  82                         os.path.join(bl, fname))
  83
  84     bus = os.path.join(bp, 'busenable.bsv')
  85     pmp = os.path.join(bp, 'pinmux.bsv')
  86     bvp = os.path.join(bp, 'bus.bsv')
  87     idef = os.path.join(bp, 'instance_defines.bsv')
  88     slow = os.path.join(bp, 'slow_peripherals.bsv')
  89     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
  90     slowmf = os.path.join(bp, 'slow_memory_map.bsv')
  91     slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
  92     fastmf = os.path.join(bp, 'fast_memory_map.bsv')
  93     fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
  94     soc = os.path.join(bp, 'socgen.bsv')
  95     soct = os.path.join(cwd, 'soc_template.bsv')
  96
  97     write_pmp(pmp, p, ifaces, iocells)
  98     write_bvp(bvp, p, ifaces)
  99     write_bus(bus, p, ifaces)
 100     write_instances(idef, p, ifaces)
 101     write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
 102     write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
 103
 104
 105 def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
 106     """ write out the slow_peripherals.bsv file.
 107         joins all the peripherals together into one AXI Lite interface
 108     """
 109     imports = ifaces.slowimport()
 110     ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
 111     regdef = ifaces.axi_reg_def()
 112     slavedecl = ifaces.axi_slave_idx()
 113     fnaddrmap = ifaces.axi_addr_map()
 114     mkslow = ifaces.mkslow_peripheral()
 115     mkcon = ifaces.mk_connection()
 116     mkcellcon = ifaces.mk_cellconn()
 117     pincon = ifaces.mk_pincon()
 118     inst = ifaces.extifinstance()
 119     inst2 = ifaces.extifinstance2()
 120     mkplic = ifaces.mk_plic()
 121     numsloirqs = ifaces.mk_sloirqsdef()
 122     ifacedef = ifaces.mk_ext_ifacedef()
 123     ifacedef = ifaces.mk_ext_ifacedef()
 124     clockcon = ifaces.mk_slowclk_con()
 125
 126     with open(slow, "w") as bsv_file:
 127         with open(slowt) as f:
 128             slowt = f.read()
 129         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
 130                                     fnaddrmap, mkslow, mkcon, mkcellcon,
 131                                     pincon, inst, mkplic,
 132                                     numsloirqs, ifacedef,
 133                                     inst2, clockcon))
 134
 135     with open(slowmf, "w") as bsv_file:
 136         with open(slowmt) as f:
 137             slowmt = f.read()
 138         bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
 139
 140
 141 def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
 142     """ write out the soc.bsv file.
 143         joins all the peripherals together as AXI Masters
 144     """
 145     ifaces.fastbusmode = True  # side-effects... shouldn't really do this
 146
 147     imports = ifaces.slowimport()
 148     ifdecl = ifaces.fastifdecl()
 149     regdef = ifaces.axi_fastmem_def()
 150     slavedecl = ifaces.axi_fastslave_idx()
 151     mastdecl = ifaces.axi_master_idx()
 152     fnaddrmap = ifaces.axi_fastaddr_map()
 153     mkfast = ifaces.mkfast_peripheral()
 154     mkcon = ifaces.mk_fast_connection()
 155     mkmstcon = ifaces.mk_master_connection()
 156     mkcellcon = ifaces.mk_cellconn()
 157     pincon = ifaces.mk_fast_pincon()
 158     inst = ifaces.extfastifinstance()
 159     mkplic = ifaces.mk_plic()
 160     numsloirqs = ifaces.mk_sloirqsdef()
 161     ifacedef = ifaces.mk_ext_ifacedef()
 162     dma = ifaces.mk_dma_irq()
 163     num_dmachannels = ifaces.num_dmachannels()
 164     clockcon = ifaces.mk_fastclk_con()
 165
 166     with open(soc, "w") as bsv_file:
 167         with open(soct) as f:
 168             soct = f.read()
 169         bsv_file.write(soct.format(imports, ifdecl, mkfast,
 170                                    slavedecl, mastdecl, mkcon,
 171                                    inst, dma, num_dmachannels,
 172                                    pincon, regdef, fnaddrmap,
 173                                    clockcon, mkmstcon,
 174                                    ))
 175
 176     with open(fastmf, "w") as bsv_file:
 177         with open(fastmt) as f:
 178             fastmt = f.read()
 179         bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap))
 180
 181
 182 def write_bus(bus, p, ifaces):
 183     # package and interface declaration followed by
 184     # the generic io_cell definition
 185     with open(bus, "w") as bsv_file:
 186         ifaces.busfmt(bsv_file)
 187
 188
 189 def write_pmp(pmp, p, ifaces, iocells):
 190     # package and interface declaration followed by
 191     # the generic io_cell definition
 192     with open(pmp, "w") as bsv_file:
 193         bsv_file.write(header)
 194
 195         bwid_template = 'Bit#(%d)'
 196         bsv_file.write('''\
 197       (*always_ready,always_enabled*)
 198       interface MuxSelectionLines;
 199
 200       // declare the method which will capture the user pin-mux
 201       // selection values.The width of the input is dependent on the number
 202       // of muxes happening per IO. For now we have a generalized width
 203       // where each IO will have the same number of muxes.''')
 204
 205         for cell in p.muxed_cells:
 206             cellnum = cell[0]
 207             bitwidth = p.get_muxbitwidth(cellnum)
 208             if bitwidth == 0:
 209                 continue
 210             cell_bit_width = bwid_template % bitwidth
 211             bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width))
 212
 213         bsv_file.write("\n      endinterface\n")
 214
 215         bsv_file.write('''
 216
 217       interface IOCellSide;
 218       // declare the interface to the IO cells.
 219       // Each IO cell will have 1 input field (output from pin mux)
 220       // and an output and out-enable field (input to pinmux)''')
 221
 222         # == create method definitions for all iocell interfaces ==#
 223         iocells.ifacefmt(bsv_file)
 224
 225         # ===== finish interface definition and start module definition=======
 226         bsv_file.write("\n      endinterface\n")
 227
 228         ifaces.ifacepfmt(bsv_file)
 229         # ===== io cell definition =======
 230         bsv_file.write('''
 231       (*always_ready,always_enabled*)
 232       interface PeripheralSide;
 233       // declare the interface to the peripherals
 234       // Each peripheral's function will be either an input, output
 235       // or be bi-directional.  an input field will be an output from the
 236       // peripheral and an output field will be an input to the peripheral.
 237       // Bi-directional functions also have an output-enable (which
 238       // again comes *in* from the peripheral)''')
 239         # ==============================================================
 240
 241         # == create method definitions for all peripheral interfaces ==#
 242         ifaces.ifacefmt2(bsv_file)
 243         bsv_file.write("\n      endinterface\n")
 244
 245         # ===== finish interface definition and start module definition=======
 246         bsv_file.write('''
 247
 248    interface Ifc_pinmux;
 249       // this interface controls how each IO cell is routed.  setting
 250       // any given IO cell's mux control value will result in redirection
 251       // of not just the input or output to different peripheral functions
 252       // but also the *direction* control - if appropriate - as well.
 253       interface MuxSelectionLines mux_lines;
 254
 255       // this interface contains the inputs, outputs and direction-control
 256       // lines for all peripherals.  GPIO is considered to also be just
 257       // a peripheral because it also has in, out and direction-control.
 258       interface PeripheralSide peripheral_side;
 259
 260       // this interface is to be linked to the individual IO cells.
 261       // if looking at a "non-muxed" GPIO design, basically the
 262       // IO cell input, output and direction-control wires are cut
 263       // (giving six pairs of dangling wires, named left and right)
 264       // these iocells are routed in their place on one side ("left")
 265       // and the matching *GPIO* peripheral interfaces in/out/dir
 266       // connect to the OTHER side ("right").  the result is that
 267       // the muxer settings end up controlling the routing of where
 268       // the I/O from the IOcell actually goes.
 269       interface IOCellSide iocell_side;
 270    endinterface
 271
 272    (*synthesize*)
 273    module mkpinmux(Ifc_pinmux);
 274 ''')
 275         # ====================================================================
 276
 277         # ======================= create wire and registers =================#
 278         bsv_file.write('''
 279       // the followins wires capture the pin-mux selection
 280       // values for each mux assigned to a CELL
 281 ''')
 282         for cell in p.muxed_cells:
 283             cellnum = cell[0]
 284             bitwidth = p.get_muxbitwidth(cellnum)
 285             if bitwidth == 0:
 286                 continue
 287             cell_bit_width = bwid_template % bitwidth
 288             bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width))
 289
 290         iocells.wirefmt(bsv_file)
 291         ifaces.wirefmt(bsv_file)
 292
 293         bsv_file.write("\n")
 294         # ====================================================================
 295         # ========================= Actual pinmuxing ========================#
 296         bsv_file.write('''
 297       /*====== This where the muxing starts for each io-cell======*/
 298       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 299       Wire#(Bit#(1)) val1<-mkDWire(1); // need a one
 300 ''')
 301         bsv_file.write(p.pinmux)
 302         bsv_file.write('''
 303       /*============================================================*/
 304 ''')
 305         # ====================================================================
 306         # ================= interface definitions for each method =============#
 307         bsv_file.write('''
 308     interface mux_lines = interface MuxSelectionLines
 309 ''')
 310         for cell in p.muxed_cells:
 311             cellnum = cell[0]
 312             bitwidth = p.get_muxbitwidth(cellnum)
 313             if bitwidth == 0:
 314                 continue
 315             cell_bit_width = bwid_template % bitwidth
 316             bsv_file.write(
 317                 mux_interface.ifacedef(
 318                     cellnum, cell_bit_width))
 319         bsv_file.write("\n    endinterface;")
 320
 321         bsv_file.write('''
 322
 323     interface iocell_side = interface IOCellSide
 324 ''')
 325         iocells.ifacedef(bsv_file)
 326         bsv_file.write("\n     endinterface;")
 327
 328         bsv_file.write('''
 329
 330      interface peripheral_side = interface PeripheralSide
 331 ''')
 332         ifaces.ifacedef2(bsv_file)
 333         bsv_file.write("\n      endinterface;")
 334
 335         bsv_file.write(footer)
 336         print("BSV file successfully generated: bsv_src/pinmux.bsv")
 337         # ======================================================================
 338
 339
 340 def write_bvp(bvp, p, ifaces):
 341     # ######## Generate bus transactors ################
 342     gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
 343               '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
 344     muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
 345         '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
 346
 347     gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
 348     muxdec = '\tMUX#({0}) mymux{1} <- mkmux();'
 349     gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
 350               '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
 351     muxifc = '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
 352         '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
 353     with open(bvp, 'w') as bsv_file:
 354         # assume here that all muxes have a 1:1 gpio
 355         cfg = []
 356         decl = []
 357         idec = []
 358         iks = sorted(ifaces.keys())
 359         for iname in iks:
 360             if not iname.startswith('gpio'):  # TODO: declare other interfaces
 361                 continue
 362             bank = iname[4:]
 363             ifc = ifaces[iname]
 364             npins = len(ifc.pinspecs)
 365             cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 366                                       0,  # USERSPACE
 367                                       bank, npins))
 368             cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
 369                                      0,  # USERSPACE
 370                                      bank, npins))
 371             decl.append(gpiodec.format(npins, bank))
 372             decl.append(muxdec .format(npins, bank))
 373             idec.append(gpioifc.format(bank))
 374             idec.append(muxifc.format(bank))
 375         print dir(ifaces)
 376         print ifaces.items()
 377         print dir(ifaces['gpioa'])
 378         print ifaces['gpioa'].pinspecs
 379         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
 380         gpiocfg = '\n'.join(cfg)
 381         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
 382     # ##################################################
 383
 384
 385 def write_instances(idef, p, ifaces):
 386     with open(idef, 'w') as bsv_file:
 387         txt = '''\
 388 `define ADDR {0}
 389 `define PADDR {2}
 390 `define DATA {1}
 391 `define Reg_width {1}
 392 `define USERSPACE 0
 393 `define RV64
 394
 395 // TODO: work out if these are needed
 396 `define PWM_AXI4Lite
 397 `define PRFDEPTH 6
 398 `define VADDR 39
 399 `define DCACHE_BLOCK_SIZE 4
 400 `define DCACHE_WORD_SIZE 8
 401 `define PERFMONITORS                            64
 402 `define DCACHE_WAYS 4
 403 `define DCACHE_TAG_BITS 20      // tag_bits = 52
 404
 405 // CLINT
 406     `define ClintBase       'h02000000
 407     `define ClintEnd        'h020BFFFF
 408
 409 `define PLIC
 410         `define PLICBase                'h0c000000
 411         `define PLICEnd         'h10000000
 412 `define INTERRUPT_PINS 64
 413
 414 `define BAUD_RATE 130
 415 `ifdef simulate
 416   `define BAUD_RATE 5 //130 //
 417 `endif
 418 '''
 419         bsv_file.write(txt.format(p.ADDR_WIDTH,
 420                                   p.DATA_WIDTH,
 421                                   p.PADDR_WIDTH))