make mux cells possible to be 1 wide
[pinmux.git] / src / parse.py
1 import math
2 import os.path
3
4
5 def missing_numbers(num_list):
6 original_list = [x for x in range(num_list[0], num_list[-1] + 1)]
7 num_list = set(num_list)
8 return (list(num_list ^ set(original_list)))
9
10
11 class Parse(object):
12 # == Parameters == #
13 N_MUX = 1 # number of selection lines for the mux per io
14 N_IO = 0
15 N_MUX_IO = 0
16 Addressing = 'WORD'
17 ADDR_WIDTH = 64 # TODO parameterise
18 PADDR_WIDTH = 32 # TODO parameterise
19 DATA_WIDTH = 64 # TODO parameterise
20 # ================ #
21
22 # Generating the number of bits for memory map #
23 lower_offset = 0
24 if Addressing == 'BYTE':
25 lower_offset = 0
26 elif Addressing == 'HWORD':
27 lower_offset = 1
28 elif Addressing == 'WORD':
29 lower_offset = 2
30 elif Addressing == 'DWORD':
31 lower_offset = 3
32 else:
33 print('ERROR: Addressing should be one of: BYTE, HWORD, WORD, DWORD')
34 exit(1)
35
36 def __init__(self, pth=None, verify=True):
37
38 max_io = 0
39 self.muxed_cells = []
40 self.dedicated_cells = []
41 self.pinnumbers = []
42
43 # == capture the number of IO cells required == #
44 fname = 'pinmap.txt'
45 if pth:
46 fname = os.path.join(pth, fname)
47 with open(fname) as pinmapfile:
48 for lineno, line in enumerate(pinmapfile):
49 line1 = line[:-1].split('\t')
50 if len(line1) <= 1:
51 continue
52 self.pinnumbers.append(int(line1[0]))
53 # XXX TODO: dedicated pins in separate file
54 #if len(line1) == 2: # dedicated
55 # self.dedicated_cells.append(line1)
56 #else:
57 for i in range(1, len(line1)):
58 # XXX HORRIBLE HACK!!
59 if line1[i].startswith('pwm'):
60 line1[i] = 'pwm%s_out' % line1[i][4:]
61 self.muxed_cells.append(line1)
62
63 self.pinnumbers = sorted(self.pinnumbers)
64 self.upper_offset = self.lower_offset + \
65 int(math.log(len(self.muxed_cells), 2))
66
67 if verify:
68 self.do_checks()
69
70 self.cell_bitwidth = self.get_cell_bit_width()
71
72 # == user info after parsing ================= #
73 self.N_IO = len(self.dedicated_cells) + len(self.muxed_cells)
74 print("Max number of IO: " + str(self.N_IO))
75 print("Muxer bit width: " + str(self.cell_bitwidth))
76 print("Muxed IOs: " + str(len(self.muxed_cells)))
77 print("Dedicated IOs: " + str(len(self.dedicated_cells)))
78
79 def do_checks(self):
80 """ Multiple checks to see if the user has not screwed up
81 """
82 missing_pins = missing_numbers(self.pinnumbers)
83
84 # Check-1: ensure no pin is present in both muxed and dedicated pins
85 for muxcell in self.muxed_cells:
86 for dedcel in self.dedicated_cells:
87 if dedcel[1] in muxcell:
88 print("ERROR: " + str(dedcel[1]) + " present \
89 in dedicated & muxed lists")
90 exit(1)
91
92 # Check-2: if pin numbering is consistent:
93 if missing_pins:
94 print("ERROR: Following pins have no assignment: " +
95 str(missing_numbers(self.pinnumbers)))
96 exit(1)
97 unique = set(self.pinnumbers)
98 duplicate = False
99 for each in unique:
100 count = self.pinnumbers.count(each)
101 if count > 1:
102 print("ERROR: Multiple assignment for pin: " + str(each))
103 duplicate = True
104 if duplicate:
105 exit(1)
106
107 # Check-3: confirm if N_* matches the instances in the pinmap
108 # ============================================================== #
109
110 # TODO
111
112 def get_cell_bit_width(self):
113 max_num_cells = 0
114 for cell in self.muxed_cells:
115 max_num_cells = max(len(cell) - 1, max_num_cells)
116 return int(math.log(max_num_cells + 1, 2))
117
118
119 if __name__ == '__main__':
120 p = Parse()
121 print (p.N_IO)