src/spec/interfaces.py

   1 #!/usr/bin/env python
   2
   3 from copy import deepcopy
   4
   5
   6 class Pinouts(object):
   7     def __init__(self):
   8         self.pins = {}
   9         self.fnspec = {}
  10
  11     def has_key(self, k):
  12         return k in self.pins
  13
  14     def add_spec(self, k, v):
  15         self.fnspec[k] = v
  16
  17     def update(self, pinidx, v):
  18         if pinidx not in self.pins:
  19             self.pins[pinidx] = v
  20         else:
  21             self.pins[pinidx].update(v)
  22
  23     def keys(self):
  24         return self.pins.keys()
  25
  26     def items(self):
  27         return self.pins.items()
  28
  29     def get(self, k):
  30         return self.pins[k]
  31
  32     def __len__(self):
  33         return len(self.pins)
  34
  35     def __delitem__(self, k):
  36         del self.pins[k]
  37
  38     def __getitem__(self, k):
  39         return self.pins[k]
  40
  41
  42 class Pins(object):
  43
  44     def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
  45                  spec=None, limit=None, origsuffix=None):
  46
  47         # function type can be in, out or inout, represented by - + *
  48         # strip function type out of each pin name
  49         self.fntype = {}
  50         for i in range(len(pingroup)):
  51             pname = pingroup[i]
  52             if not pname:
  53                 continue
  54             fntype = pname[-1]
  55             if fntype not in '+-*':
  56                 continue
  57             pname = pname[:-1]
  58             fntype = {'-': 'in', '+': 'out', '*': 'inout'}[fntype]
  59             self.fntype[pname] = fntype
  60             pingroup[i] = pname
  61
  62         self.fname = fname
  63         self.pingroup = pingroup
  64         self.bankspec = bankspec
  65         self.suffix = suffix
  66         self.origsuffix = origsuffix or suffix
  67         self.bank = bank
  68         self.mux = mux
  69
  70         # create consistent name suffixes
  71         pingroup = namesuffix(fname, suffix, pingroup)
  72         suffix = ''  # hack
  73
  74         res = {}
  75         names = {}
  76         idx = 0
  77         for name in pingroup[:limit]:
  78             if suffix and name:
  79                 name_ = "%s_%s" % (name, suffix)
  80             else:
  81                 name_ = name
  82             if spec and name in spec:
  83                 continue
  84             pin = {mux: (name_, bank)}
  85             offs_bank, offs_ = offs
  86             idx_ = offs_ + idx
  87             idx += 1
  88             idx_ += bankspec[bank]
  89             res[idx_] = pin
  90             names[name] = idx_
  91         for name in pingroup:
  92             if suffix and name:
  93                 name_ = "%s_%s" % (name, suffix)
  94             else:
  95                 name_ = name
  96             if not spec:
  97                 continue
  98             if name not in spec:
  99                 continue
 100             idx_, mux_, bank_ = spec[name]
 101             idx_ = names[idx_]
 102             pin = {mux_: (name_, bank_)}
 103             if idx_ in res:
 104                 res[idx_].update(pin)
 105             else:
 106                 res[idx_] = pin
 107
 108         self.pins = res
 109
 110
 111 def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 112     i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
 113     # for i in range(4):
 114     #    i2spins.append("DO%d+" % i)
 115     return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
 116                 origsuffix=suffix)
 117
 118
 119 def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
 120     emmcpins = ['CMD+', 'CLK+']
 121     for i in range(8):
 122         emmcpins.append("D%d*" % i)
 123     return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
 124                 origsuffix=suffix)
 125
 126
 127 def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
 128           start=None, limit=None):
 129     sdmmcpins = ['CMD+', 'CLK+']
 130     for i in range(4):
 131         sdmmcpins.append("D%d*" % i)
 132     sdmmcpins = sdmmcpins[start:limit]
 133     return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
 134                 origsuffix=suffix)
 135
 136
 137 def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
 138     spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
 139     return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
 140                 origsuffix=suffix)
 141
 142
 143 def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 144     spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
 145     return Pins(
 146         'QSPI',
 147         spipins,
 148         bankspec,
 149         suffix,
 150         offs,
 151         bank,
 152         mux,
 153         spec,
 154         limit,
 155         origsuffix=suffix)
 156
 157
 158 def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
 159     spipins = ['SDA*', 'SCL*']
 160     return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
 161                 origsuffix=suffix)
 162
 163
 164 def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
 165     jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
 166     return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
 167                 origsuffix=suffix)
 168
 169
 170 def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
 171     uartpins = ['TX+', 'RX-']
 172     return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
 173                 origsuffix=suffix)
 174
 175
 176 def namesuffix(name, suffix, namelist):
 177     names = []
 178     for n in namelist:
 179         if n:
 180             names.append("%s%s_%s" % (name, suffix, n))
 181         else:
 182             names.append("%s_%s" % (name, suffix))
 183     return names
 184
 185
 186 def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
 187     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 188     for i in range(8):
 189         ulpipins.append('D%d*' % i)
 190     return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
 191                 origsuffix=suffix)
 192
 193
 194 def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
 195     uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
 196     return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
 197                 origsuffix=suffix)
 198
 199
 200 def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
 201     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 202     for i in range(24):
 203         ttlpins.append("D%d+" % i)
 204     return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
 205                 origsuffix=suffix)
 206
 207
 208 def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
 209     buspins = []
 210     for i in range(4):
 211         buspins.append("ERXD%d-" % i)
 212     for i in range(4):
 213         buspins.append("ETXD%d+" % i)
 214     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 215                 'EMDC+', 'EMDIO*',
 216                 'ETXEN+', 'ETXCK+', 'ECRS-',
 217                 'ECOL+', 'ETXERR+']
 218     return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
 219                 origsuffix=suffix)
 220
 221
 222 def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 223     buspins = []
 224     for i in range(8):
 225         buspins.append("AD%d*" % i)
 226     for i in range(2):
 227         buspins.append("CS%d+" % i)
 228     buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
 229                 'A0', 'A1', 'TS', 'TBST',
 230                 'TSIZ0', 'TSIZ1']
 231     for i in range(4):
 232         buspins.append("BWE%d" % i)
 233     for i in range(2, 6):
 234         buspins.append("CS%d+" % i)
 235     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 236                 origsuffix=suffix)
 237
 238
 239 def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 240     buspins = []
 241     for i in range(8, 32):
 242         buspins.append("AD%d*" % i)
 243     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 244                 origsuffix=suffix)
 245
 246
 247 def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
 248     buspins = []
 249     for i in range(16):
 250         buspins.append("SDRDQM%d*" % i)
 251     for i in range(12):
 252         buspins.append("SDRAD%d+" % i)
 253     for i in range(8):
 254         buspins.append("SDRDQ%d+" % i)
 255     for i in range(3):
 256         buspins.append("SDRCS%d#+" % i)
 257     for i in range(2):
 258         buspins.append("SDRDQ%d+" % i)
 259     for i in range(2):
 260         buspins.append("SDRBA%d+" % i)
 261     buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
 262                 'SDRRST+']
 263     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
 264                 origsuffix=suffix)
 265
 266
 267 def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 268     buspins = []
 269     for i in range(3, 6):
 270         buspins.append("SDRCS%d#+" % i)
 271     for i in range(8, 32):
 272         buspins.append("SDRDQ%d*" % i)
 273     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 274                 origsuffix=suffix)
 275
 276
 277 def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
 278     buspins = []
 279     for i in range(8):
 280         buspins.append("MCUD%d*" % i)
 281     for i in range(8):
 282         buspins.append("MCUAD%d+" % (i + 8))
 283     for i in range(6):
 284         buspins.append("MCUCS%d+" % i)
 285     for i in range(2):
 286         buspins.append("MCUNRB%d+" % i)
 287     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 288                 'MCURST+']
 289     return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
 290                 origsuffix=suffix)
 291
 292
 293 def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
 294              spec=None):
 295     gpiopins = []
 296     for i in range(gpiooffs, gpiooffs + gpionum):
 297         gpiopins.append("%s%d*" % (bank, i))
 298     return Pins(prefix, gpiopins, bankspec, suffix, offs, bank, mux, spec,
 299                 origsuffix=suffix)
 300
 301
 302 def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 303     gpiopins = []
 304     for i in range(gpiooffs, gpiooffs + gpionum):
 305         gpiopins.append("%d*" % (i))
 306     return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
 307                 origsuffix=suffix)
 308
 309
 310 def pwm(bankspec, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None):
 311     pwmpins = []
 312     for i in range(pwmoffs, pwmoffs + pwmnum):
 313         pwmpins.append("%d+" % (i))
 314     return Pins('PWM', pwmpins, bankspec, suffix, offs, bank, mux, spec,
 315                 origsuffix=suffix)
 316
 317
 318 def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 319     return _pinbank(bankspec, "GPIO%s" % bank, suffix, offs, bank, gpiooffs,
 320                               gpionum, mux=0, spec=None)
 321
 322
 323 def pinmerge(pins, fn):
 324     # hack, store the function specs in the pins dict
 325     fname = fn.fname
 326     suffix = fn.origsuffix
 327     bank = fn.bank
 328
 329     if not hasattr(pins, 'fnspec'):
 330         pins.fnspec = pins
 331     if fname == 'GPIO':
 332         fname = fname + bank
 333     assert 'EINT' not in pins
 334     if fname not in pins.fnspec:
 335         pins.add_spec(fname, {})
 336     print "fname bank suffix", fname, bank, suffix
 337     if suffix or fname == 'EINT' or fname == 'PWM':
 338         specname = fname + suffix
 339     else:
 340         specname = fname + bank
 341     if specname in pins.fnspec[fname]:
 342         # ok so some declarations may bring in different
 343         # names at different stages (EINT, PWM, flexbus1/2)
 344         # so we have to merge the names in.  main thing is
 345         # the pingroup
 346         tomerge = pins.fnspec[fname][specname]
 347         for p in fn.pingroup:
 348             if p not in tomerge.pingroup:
 349                 tomerge.pingroup.append(p)
 350         tomerge.pins.update(fn.pins)
 351         tomerge.fntype.update(fn.fntype)
 352     else:
 353         pins.fnspec[fname][specname] = deepcopy(fn)
 354
 355     # merge actual pins
 356     for (pinidx, v) in fn.pins.items():
 357         pins.update(pinidx, v)