src/spec/interfaces.py

   1 #!/usr/bin/env python
   2
   3 from copy import deepcopy
   4
   5
   6 class Pinouts(object):
   7     def __init__(self):
   8         self.pins = {}
   9         self.fnspec = {}
  10
  11     def has_key(self, k):
  12         return self.pins.has_key(k)
  13
  14     def add_spec(self, k, v):
  15         self.fnspec[k] = v
  16
  17     def update(self, pinidx, v):
  18         if not self.pins.has_key(pinidx):
  19             self.pins[pinidx] = v
  20         else:
  21             self.pins[pinidx].update(v)
  22
  23     def keys(self):
  24         return self.pins.keys()
  25
  26     def items(self):
  27         return self.pins.items()
  28
  29     def get(self, k):
  30         return self.pins[k]
  31
  32     def __len__(self):
  33         return len(self.pins)
  34
  35     def __delitem__(self, k):
  36         del self.pins[k]
  37
  38     def __getitem__(self, k):
  39         return self.pins[k]
  40
  41
  42 class Pins(object):
  43
  44     def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
  45              spec=None, limit=None, origsuffix=None):
  46
  47         # function type can be in, out or inout, represented by - + *
  48         # strip function type out of each pin name
  49         self.fntype = {}
  50         for i in range(len(pingroup)):
  51             pname = pingroup[i]
  52             if not pname:
  53                 continue
  54             fntype = pname[-1]
  55             if fntype not in '+-*':
  56                 continue
  57             pname = pname[:-1]
  58             fntype = {'-': 'in', '+': 'out', '*': 'inout'}[fntype]
  59             self.fntype[pname] = fntype
  60             pingroup[i] = pname
  61
  62         self.fname = fname
  63         self.pingroup = pingroup
  64         self.bankspec = bankspec
  65         self.suffix = suffix
  66         self.origsuffix = origsuffix or suffix
  67         self.bank = bank
  68         self.mux = mux
  69
  70         # create consistent name suffixes
  71         pingroup = namesuffix(fname, suffix, pingroup)
  72         suffix = '' # hack
  73
  74         res = {}
  75         names = {}
  76         idx = 0
  77         for name in pingroup[:limit]:
  78             if suffix and name:
  79                 name_ = "%s_%s" % (name, suffix)
  80             else:
  81                 name_ = name
  82             if spec and spec.has_key(name):
  83                 continue
  84             pin = {mux: (name_, bank)}
  85             offs_bank, offs_ = offs
  86             idx_ = offs_ + idx
  87             idx += 1
  88             idx_ += bankspec[bank]
  89             res[idx_] = pin
  90             names[name] = idx_
  91         for name in pingroup:
  92             if suffix and name:
  93                 name_ = "%s_%s" % (name, suffix)
  94             else:
  95                 name_ = name
  96             if not spec:
  97                 continue
  98             if not spec.has_key(name):
  99                 continue
 100             idx_, mux_, bank_ = spec[name]
 101             idx_ = names[idx_]
 102             pin = {mux_: (name_, bank_)}
 103             if res.has_key(idx_):
 104                 res[idx_].update(pin)
 105             else:
 106                 res[idx_] = pin
 107
 108         self.pins = res
 109
 110
 111 def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 112     i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
 113     #for i in range(4):
 114     #    i2spins.append("DO%d+" % i)
 115     return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
 116                 origsuffix=suffix)
 117
 118 def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
 119     emmcpins = ['CMD+', 'CLK+']
 120     for i in range(8):
 121         emmcpins.append("D%d*" % i)
 122     return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
 123                 origsuffix=suffix)
 124
 125 def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
 126                 start=None, limit=None):
 127     sdmmcpins = ['CMD+', 'CLK+']
 128     for i in range(4):
 129         sdmmcpins.append("D%d*" % i)
 130     sdmmcpins = sdmmcpins[start:limit]
 131     return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
 132                 origsuffix=suffix)
 133
 134 def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
 135     spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
 136     return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
 137                 origsuffix=suffix)
 138
 139 def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 140     spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
 141     return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit,
 142                 origsuffix=suffix)
 143
 144 def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
 145     spipins = ['SDA*', 'SCL*']
 146     return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
 147                 origsuffix=suffix)
 148
 149 def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
 150     jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
 151     return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
 152                 origsuffix=suffix)
 153
 154 def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
 155     uartpins = ['TX+', 'RX-']
 156     return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
 157                 origsuffix=suffix)
 158
 159 def namesuffix(name, suffix, namelist):
 160     names = []
 161     for n in namelist:
 162         if n:
 163             names.append("%s%s_%s" % (name, suffix, n))
 164         else:
 165             names.append("%s_%s" % (name, suffix))
 166     return names
 167
 168 def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
 169     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 170     for i in range(8):
 171         ulpipins.append('D%d*' % i)
 172     return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
 173                 origsuffix=suffix)
 174
 175 def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
 176     uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
 177     return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
 178                 origsuffix=suffix)
 179
 180 def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
 181     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 182     for i in range(24):
 183         ttlpins.append("D%d+" % i)
 184     return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
 185                 origsuffix=suffix)
 186
 187 def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
 188     buspins = []
 189     for i in range(4):
 190         buspins.append("ERXD%d-" % i)
 191     for i in range(4):
 192         buspins.append("ETXD%d+" % i)
 193     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 194                 'EMDC+', 'EMDIO*',
 195                 'ETXEN+', 'ETXCK+', 'ECRS-',
 196                 'ECOL+', 'ETXERR+']
 197     return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
 198                 origsuffix=suffix)
 199
 200 def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 201     buspins = []
 202     for i in range(8):
 203         buspins.append("AD%d*" % i)
 204     for i in range(2):
 205         buspins.append("CS%d+" % i)
 206     buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
 207                 'A0', 'A1', 'TS', 'TBST',
 208                 'TSIZ0', 'TSIZ1']
 209     for i in range(4):
 210         buspins.append("BWE%d" % i)
 211     for i in range(2,6):
 212         buspins.append("CS%d+" % i)
 213     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 214                 origsuffix=suffix)
 215
 216 def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 217     buspins = []
 218     for i in range(8,32):
 219         buspins.append("AD%d*" % i)
 220     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 221                 origsuffix=suffix)
 222
 223 def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
 224     buspins = []
 225     for i in range(16):
 226         buspins.append("SDRDQM%d*" % i)
 227     for i in range(12):
 228         buspins.append("SDRAD%d+" % i)
 229     for i in range(8):
 230         buspins.append("SDRDQ%d+" % i)
 231     for i in range(3):
 232         buspins.append("SDRCS%d#+" % i)
 233     for i in range(2):
 234         buspins.append("SDRDQ%d+" % i)
 235     for i in range(2):
 236         buspins.append("SDRBA%d+" % i)
 237     buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
 238                 'SDRRST+']
 239     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
 240                 origsuffix=suffix)
 241
 242 def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
 243     buspins = []
 244     for i in range(3,6):
 245         buspins.append("SDRCS%d#+" % i)
 246     for i in range(8,32):
 247         buspins.append("SDRDQ%d*" % i)
 248     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
 249                 origsuffix=suffix)
 250
 251 def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
 252     buspins = []
 253     for i in range(8):
 254         buspins.append("MCUD%d*" % i)
 255     for i in range(8):
 256         buspins.append("MCUAD%d+" % (i+8))
 257     for i in range(6):
 258         buspins.append("MCUCS%d+" % i)
 259     for i in range(2):
 260         buspins.append("MCUNRB%d+" % i)
 261     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 262                 'MCURST+']
 263     return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
 264                 origsuffix=suffix)
 265
 266 def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
 267              spec=None):
 268     gpiopins = []
 269     for i in range(gpiooffs, gpiooffs+gpionum):
 270         gpiopins.append("%s%d*" % (bank, i))
 271     return Pins(prefix, gpiopins, bankspec, suffix, offs, bank, mux, spec,
 272                 origsuffix=suffix)
 273
 274 def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 275     gpiopins = []
 276     for i in range(gpiooffs, gpiooffs+gpionum):
 277         gpiopins.append("%d*" % (i))
 278     return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
 279                 origsuffix=suffix)
 280
 281 def pwm(bankspec, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None):
 282     pwmpins = []
 283     for i in range(pwmoffs, pwmoffs+pwmnum):
 284         pwmpins.append("%d+" % (i))
 285     return Pins('PWM', pwmpins, bankspec, suffix, offs, bank, mux, spec,
 286                 origsuffix=suffix)
 287
 288 def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
 289     return _pinbank(bankspec, "GPIO%s" % bank, suffix, offs, bank, gpiooffs,
 290                               gpionum, mux=0, spec=None)
 291
 292 def pinmerge(pins, fn):
 293     # hack, store the function specs in the pins dict
 294     fname = fn.fname
 295     suffix = fn.origsuffix
 296     bank = fn.bank
 297
 298     if not hasattr(pins, 'fnspec'):
 299         pins.fnspec = pins
 300     if fname == 'GPIO':
 301         fname = fname + bank
 302     assert not pins.has_key('EINT')
 303     if not pins.fnspec.has_key(fname):
 304         pins.add_spec(fname, {})
 305     print "fname bank suffix", fname, bank, suffix
 306     if suffix or fname == 'EINT' or fname == 'PWM':
 307         specname = fname + suffix
 308     else:
 309         specname = fname + bank
 310     if pins.fnspec[fname].has_key(specname):
 311         # ok so some declarations may bring in different
 312         # names at different stages (EINT, PWM, flexbus1/2)
 313         # so we have to merge the names in.  main thing is
 314         # the pingroup
 315         tomerge = pins.fnspec[fname][specname]
 316         for p in fn.pingroup:
 317             if p not in tomerge.pingroup:
 318                 tomerge.pingroup.append(p)
 319         tomerge.pins.update(fn.pins)
 320         tomerge.fntype.update(fn.fntype)
 321     else:
 322         pins.fnspec[fname][specname] = deepcopy(fn)
 323
 324     # merge actual pins
 325     for (pinidx, v) in fn.pins.items():
 326         pins.update(pinidx, v)
 327