src/spec/iomux.py

   1 """This is the module used for multiplexing IO signals
   2
   3 Documentation: https://libre-soc.org/docs/pinmux/temp_pinmux_info/
   4 Bug: https://bugs.libre-soc.org/show_bug.cgi?id=762
   5 """
   6 #from random import randint
   7 from nmigen import Elaboratable, Module, Signal, Record, Array
   8 #from nmigen.utils import log2_int
   9 from nmigen.cli import rtlil
  10 #from soc.minerva.wishbone import make_wb_layout
  11 from nmutil.util import wrap
  12 #from soc.bus.test.wb_rw import wb_read, wb_write
  13
  14 cxxsim = False
  15 if cxxsim:
  16     from nmigen.sim.cxxsim import Simulator, Settle
  17 else:
  18     from nmigen.sim import Simulator, Settle
  19
  20 class IOMuxBlock(Elaboratable):
  21
  22     def __init__(self):
  23         self.bank_sel = Signal()
  24
  25         self.portin0 = {"i": Signal(), "o": Signal(), "oe": Signal()}
  26         self.portin1 = {"i": Signal(), "o": Signal(), "oe": Signal()}
  27         self.portout = {"i": Signal(), "o": Signal(), "oe": Signal()}
  28
  29     def elaborate(self, platform):
  30         m = Module()
  31         comb, sync = m.d.comb, m.d.sync
  32
  33         bank_sel = self.bank_sel
  34         portin0 = self.portin0
  35         portin1 = self.portin1
  36         portout = self.portout
  37         # Connect IO Pad output port to one of the peripheral IOs
  38         comb += portout["o"].eq(Mux(bank_sel, portin1["o"], portin0["o"]))
  39         comb += portout["oe"].eq(Mux(bank_sel, portin1["oe"], portin0["oe"]))
  40
  41         # Connect peripheral inputs to the IO pad input
  42         comb += portin0["i"].eq(Mux(bank_sel, 0, portout["i"]))
  43         comb += portin1["i"].eq(Mux(bank_sel, portout["i"], 0))
  44
  45         return m
  46
  47     def ports(self):
  48         return list(self)
  49
  50 def sim_iomux(dut):
  51     # start by setting portin0
  52     dut.portin0["o"].eq(1)
  53     dut.portin0["oe"].eq(1)
  54     yield
  55     dut.portout["i"].eq(1)
  56
  57     print("Finished the IO mux block test!")
  58
  59 def test_iomux():
  60
  61     dut = IOMuxBlock()
  62     vl = rtlil.convert(dut, ports=dut.ports())
  63     with open("test_gpio.il", "w") as f:
  64         f.write(vl)
  65
  66     m = Module()
  67
  68     #sim = Simulator(m)
  69     #sim.add_clock(1e-6)
  70
  71     #sim.add_sync_process(wrap(sim_gpio(dut)))
  72     #sim_writer = sim.write_vcd('test_gpio.vcd')
  73     #with sim_writer:
  74     #    sim.run()
  75
  76
  77 if __name__ == '__main__':
  78     test_iomux()
  79