src/spec/jtag.py

   1 """JTAG interface
   2
   3 using Staf Verhaegen (Chips4Makers) wishbone TAP
   4 """
   5
   6 from collections import OrderedDict
   7 from nmigen import (Module, Signal, Elaboratable, Cat)
   8 from nmigen.cli import rtlil
   9 from c4m.nmigen.jtag.tap import IOType, TAP
  10
  11 # map from pinmux to c4m jtag iotypes
  12 iotypes = {'-': IOType.In,
  13            '+': IOType.Out,
  14            '>': IOType.TriOut,
  15            '*': IOType.InTriOut,
  16         }
  17
  18 scanlens = {IOType.In: 1,
  19            IOType.Out: 1,
  20            IOType.TriOut: 2,
  21            IOType.InTriOut: 3,
  22             }
  23
  24 def dummy_pinset():
  25     # sigh this needs to come from pinmux.
  26     gpios = []
  27     for i in range(16):
  28         gpios.append("%d*" % i)
  29     return {'uart': ['tx+', 'rx-'],
  30              'gpio': gpios,
  31              'i2c': ['sda*', 'scl+']}
  32
  33 # TODO: move to suitable location
  34 class Pins:
  35     """declare a list of pins, including name and direction.  grouped by fn
  36     the pin dictionary needs to be in a reliable order so that the JTAG
  37     Boundary Scan is also in a reliable order
  38     """
  39     def __init__(self, pindict):
  40         self.io_names = OrderedDict()
  41         if isinstance(pindict, OrderedDict):
  42             self.io_names.update(pindict)
  43         else:
  44             keys = list(pindict.keys())
  45             keys.sort()
  46             for k in keys:
  47                 self.io_names[k] = pindict[k]
  48
  49     def __iter__(self):
  50         # start parsing io_names and enumerate them to return pin specs
  51         scan_idx = 0
  52         for fn, pins in self.io_names.items():
  53             for pin in pins:
  54                 # decode the pin name and determine the c4m jtag io type
  55                 name, pin_type = pin[:-1], pin[-1]
  56                 iotype = iotypes[pin_type]
  57                 pin_name = "%s_%s" % (fn, name)
  58                 yield (fn, name, iotype, pin_name, scan_idx)
  59                 scan_idx += scanlens[iotype] # inc boundary reg scan offset
  60
  61
  62 class JTAG(TAP, Pins):
  63     # 32-bit data width here so that it matches with litex
  64     def __init__(self, pinset, domain, wb_data_wid=32):
  65         self.domain = domain
  66         TAP.__init__(self, ir_width=4)
  67         Pins.__init__(self, pinset)
  68
  69         # enumerate pin specs and create IOConn Records.
  70         # we store the boundary scan register offset in the IOConn record
  71         self.ios = [] # these are enumerated in external_ports
  72         self.scan_len = 0
  73         for fn, pin, iotype, pin_name, scan_idx in list(self):
  74             io = self.add_io(iotype=iotype, name=pin_name)
  75             io._scan_idx = scan_idx # hmm shouldn't really do this
  76             self.scan_len += scan_idx # record full length of boundary scan
  77             self.ios.append(io)
  78
  79         # this is redundant.  or maybe part of testing, i don't know.
  80         self.sr = self.add_shiftreg(ircode=4, length=3,
  81                                     domain=domain)
  82
  83         # create and connect wishbone
  84         self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
  85                                    address_width=30, data_width=wb_data_wid,
  86                                    granularity=8, # 8-bit wide
  87                                    name="jtag_wb",
  88                                    domain=domain)
  89
  90         # create DMI2JTAG (goes through to dmi_sim())
  91         self.dmi = self.add_dmi(ircodes=[8, 9, 10],
  92                                     domain=domain)
  93
  94         # use this for enable/disable of parts of the ASIC.
  95         # XXX make sure to add the _en sig to en_sigs list
  96         self.wb_icache_en = Signal(reset=1)
  97         self.wb_dcache_en = Signal(reset=1)
  98         self.wb_sram_en = Signal(reset=1)
  99         self.en_sigs = en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
 100                                      self.wb_sram_en)
 101         self.sr_en = self.add_shiftreg(ircode=11, length=len(en_sigs),
 102                                        domain=domain)
 103
 104     def elaborate(self, platform):
 105         m = super().elaborate(platform)
 106         m.d.comb += self.sr.i.eq(self.sr.o) # loopback as part of test?
 107
 108         # provide way to enable/disable wishbone caches and SRAM
 109         # just in case of issues
 110         # see https://bugs.libre-soc.org/show_bug.cgi?id=520
 111         with m.If(self.sr_en.oe):
 112             m.d.sync += self.en_sigs.eq(self.sr_en.o)
 113         # also make it possible to read the enable/disable current state
 114         with m.If(self.sr_en.ie):
 115             m.d.comb += self.sr_en.i.eq(self.en_sigs)
 116
 117         # create a fake "stall"
 118         #wb = self.wb
 119         #m.d.comb += wb.stall.eq(wb.cyc & ~wb.ack) # No burst support
 120
 121         return m
 122
 123     def external_ports(self):
 124         """create a list of ports that goes into the top level il (or verilog)
 125         """
 126         ports = super().external_ports()           # gets JTAG signal names
 127         ports += list(self.wb.fields.values())     # wishbone signals
 128         for io in self.ios:
 129             ports += list(io.core.fields.values()) # io "core" signals
 130             ports += list(io.pad.fields.values())  # io "pad" signals"
 131         return ports
 132
 133
 134 if __name__ == '__main__':
 135     pinset = dummy_pinset()
 136     dut = JTAG(pinset, "sync")
 137
 138     vl = rtlil.convert(dut)
 139     with open("test_jtag.il", "w") as f:
 140         f.write(vl)
 141