src/spec/ls2.py

   1 #!/usr/bin/env python
   2 # see https://bugs.libre-soc.org/show_bug.cgi?id=739
   3
   4 from spec.base import PinSpec
   5 from parse import Parse
   6
   7 from pprint import pprint
   8 from spec.ifaceprint import display, display_fns, check_functions
   9 from spec.ifaceprint import display_fixed
  10 from collections import OrderedDict
  11
  12 def pinspec():
  13     pinbanks = OrderedDict((
  14         ('N', (32, 4)),
  15         ('E', (32, 4)),
  16         ('S', (32, 4)),
  17         ('W', (32, 4)),
  18     ))
  19     fixedpins = {
  20         'CTRL_SYS': [
  21             'TEST',
  22             'JTAG_SEL',
  23             'UBOOT_SEL',
  24             'NMI#',
  25             'RESET#',
  26             'CLK24M_IN',
  27             'CLK24M_OUT',
  28             'PLLTEST',
  29             'PLLREGIO',
  30             'PLLVP25',
  31             'PLLDV',
  32             'PLLVREG',
  33             'PLLGND',
  34         ],
  35         'POWER_GPIO': [
  36             'VDD_GPIOB',
  37             'GND_GPIOB',
  38         ]}
  39     fixedpins = {}
  40     function_names = {
  41                       'RG0': 'Gigabit Ethernet 0',
  42                       'PWM': 'PWM (pulse-width modulation)',
  43                       'MSPI0': 'SPI Master 1 (general)',
  44                       'MSPI1': 'SPI Master 2 (SDCard)',
  45                       'UART0': 'UART (TX/RX) 1',
  46                       'SYS': 'System Control',
  47                       'GPIO': 'GPIO',
  48                       'EINT': 'External Interrupt',
  49                       'PWM': 'PWM',
  50                       'JTAG': 'JTAG',
  51                       'MTWI': 'I2C Master 1',
  52                       'SD0': 'SD/MMC 1',
  53                       'SDR': 'SDRAM',
  54                       'VDD': 'Power',
  55                       'VSS': 'GND',
  56                       #'LPC1': 'Low Pincount Interface 1',
  57                       #'LPC2': 'Low Pincount Interface 2',
  58                       }
  59
  60     ps = PinSpec(pinbanks, fixedpins, function_names)
  61
  62     ps.sdram1("", ('W', 0), 0, 15, 6, rev=True) # AD4-9, turned round
  63     ps.vdd("E", ('W', 6), 0, 0, 1)
  64     ps.vss("E", ('W', 7), 0, 0, 1)
  65     ps.vdd("I", ('W', 8), 0, 0, 1)
  66     ps.vss("I", ('W', 9), 0, 0, 1)
  67     ps.sdram1("", ('W', 10), 0, 0, 15, rev=True) # SDRAM DAM0, D0-7, AD0-3
  68     ps.mi2c("", ('W', 26), 0, 0, 2)
  69     ps.vss("I", ('W', 28), 0, 1, 1)
  70     ps.vdd("I", ('W', 29), 0, 1, 1)
  71     ps.vss("E", ('W', 30), 0, 1, 1)
  72     ps.vdd("E", ('W', 31), 0, 1, 1)
  73
  74     ps.sdram2("", ('S', 0), 0, 0, 4) # 1st 4, AD10-12,DQM1
  75     ps.vdd("E", ('S', 4), 0, 2, 1)
  76     ps.vss("E", ('S', 5), 0, 2, 1)
  77     ps.vdd("I", ('S', 6), 0, 2, 1)
  78     ps.vss("I", ('S', 7), 0, 2, 1)
  79     ps.sdram2("", ('S', 8), 0, 4, 8) # D8-15
  80     ps.sdram1("", ('S', 16), 0, 21, 9) # clk etc.
  81     ps.vss("I", ('S', 22), 0, 3, 1)
  82     ps.vdd("I", ('S', 23), 0, 3, 1)
  83     ps.vss("E", ('S', 24), 0, 3, 1)
  84     ps.vdd("E", ('S', 25), 0, 3, 1)
  85     ps.uart("0", ('S', 26), 0)
  86     ps.mspi("0", ('S', 28), 0)
  87
  88     ps.gpio("", ('E', 0), 0, 0, 4) # GPIO 0-3
  89     ps.rgmii("1", ('E', 0), 1, 0, 4) # RXD0-3
  90     ps.vss("E", ('E', 4), 0, 4, 1)
  91     ps.vdd("E", ('E', 5), 0, 4, 1)
  92     ps.vdd("I", ('E', 6), 0, 4, 1)
  93     ps.vss("I", ('E', 7), 0, 4, 1)
  94     ps.gpio("", ('E', 8), 0, 6, 10) # GPIO 4-13
  95     ps.rgmii("1", ('E', 8), 1, 4, 10) # more RGMII-2
  96     ps.jtag("", ('E', 18), 0, 0, 4)
  97     ps.vss("I", ('E', 22), 0, 5, 1)
  98     ps.vdd("I", ('E', 23), 0, 5, 1)
  99     ps.vss("E", ('E', 24), 0, 5, 1)
 100     ps.vdd("E", ('E', 25), 0, 5, 1)
 101     ps.gpio("", ('E', 26), 0, 14, 4) # GPIO 14-17
 102     ps.rgmii("1", ('E', 26), 1, 14, 5) # more RGMII-2
 103     ps.eint("", ('E', 28), 2, 0, 2)
 104     ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
 105
 106     ps.rgmii("0", ('N', 0), 0, 0, 4)
 107     ps.vss("E", ('N', 4), 0, 6, 1)
 108     ps.vdd("E", ('N', 5), 0, 6, 1)
 109     ps.vdd("I", ('N', 6), 0, 6, 1)
 110     ps.vss("I", ('N', 7), 0, 6, 1)
 111     ps.rgmii("0", ('N', 8), 0, 0, 14)
 112     #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
 113     #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
 114     #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
 115     ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
 116     ps.vss("I", ('N', 23), 0, 7, 1)
 117     ps.vdd("I", ('N', 24), 0, 7, 1)
 118     ps.vss("E", ('N', 25), 0, 7, 1)
 119     ps.vdd("E", ('N', 26), 0, 7, 1)
 120
 121     #ps.mquadspi("1", ('S', 0), 0)
 122
 123     print ("ps clocks", ps.clocks)
 124
 125     # Scenarios below can be spec'd out as either "find first interface"
 126     # by name/number e.g. SPI1, or as "find in bank/mux" which must be
 127     # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
 128     # EINT and PWM are grouped together, specially, but may still be spec'd
 129     # using "BM:Name".  Pins are removed in-order as listed from
 130     # lists (interfaces, EINTs, PWMs) from available pins.
 131
 132     ls180 = [
 133             # 'SD0', litex problem 25mar2021
 134             'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
 135              'VDD', 'VSS', 'SYS',
 136                 'MTWI', 'MSPI0',
 137                 # 'MSPI1', litex problem 25mar2021
 138                 'SDR']
 139     ls180_eint = []
 140     ls180_pwm = []#['B0:PWM_0']
 141     descriptions = {
 142         'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
 143         'and UART2, for debug purposes',
 144         'MTWI': 'I2C.\n',
 145         'E2:SD1': '',
 146         'MSPI1': '',
 147         'UART0': '',
 148         'LPC1': '',
 149         'SYS': '',
 150         'LPC2': '',
 151         'SDR': '',
 152         'B1:LCD/22': '18-bit RGB/TTL LCD',
 153         'ULPI0/8': 'user-facing: internal (on Card), USB-OTG ULPI PHY',
 154         'ULPI1': 'dual USB2 Host ULPI PHY'
 155     }
 156
 157     ps.add_scenario("Libre-SOC 2 (NGI Router) 180nm", ls180, ls180_eint,
 158                     ls180_pwm, descriptions)
 159
 160     return ps