2 # see https://bugs.libre-soc.org/show_bug.cgi?id=739
4 from spec
.base
import PinSpec
5 from parse
import Parse
7 from pprint
import pprint
8 from spec
.ifaceprint
import display
, display_fns
, check_functions
9 from spec
.ifaceprint
import display_fixed
10 from collections
import OrderedDict
13 pinbanks
= OrderedDict((
41 'RG0': 'Gigabit Ethernet 0',
42 'PWM': 'PWM (pulse-width modulation)',
43 'MSPI0': 'SPI Master 1 (general)',
44 'MSPI1': 'SPI Master 2 (SDCard)',
45 'UART0': 'UART (TX/RX) 1',
46 'SYS': 'System Control',
48 'EINT': 'External Interrupt',
51 'MTWI': 'I2C Master 1',
56 #'LPC1': 'Low Pincount Interface 1',
57 #'LPC2': 'Low Pincount Interface 2',
60 ps
= PinSpec(pinbanks
, fixedpins
, function_names
)
62 ps
.sdram1("", ('W', 0), 0, 15, 6, rev
=True) # AD4-9, turned round
63 ps
.vdd("E", ('W', 6), 0, 0, 1)
64 ps
.vss("E", ('W', 7), 0, 0, 1)
65 ps
.vdd("I", ('W', 8), 0, 0, 1)
66 ps
.vss("I", ('W', 9), 0, 0, 1)
67 ps
.sdram1("", ('W', 10), 0, 0, 15, rev
=True) # SDRAM DAM0, D0-7, AD0-3
68 ps
.mi2c("", ('W', 26), 0, 0, 2)
69 ps
.vss("I", ('W', 28), 0, 1, 1)
70 ps
.vdd("I", ('W', 29), 0, 1, 1)
71 ps
.vss("E", ('W', 30), 0, 1, 1)
72 ps
.vdd("E", ('W', 31), 0, 1, 1)
74 ps
.sdram2("", ('S', 0), 0, 0, 4) # 1st 4, AD10-12,DQM1
75 ps
.vdd("E", ('S', 4), 0, 2, 1)
76 ps
.vss("E", ('S', 5), 0, 2, 1)
77 ps
.vdd("I", ('S', 6), 0, 2, 1)
78 ps
.vss("I", ('S', 7), 0, 2, 1)
79 ps
.sdram2("", ('S', 8), 0, 4, 8) # D8-15
80 ps
.sdram1("", ('S', 16), 0, 21, 9) # clk etc.
81 ps
.vss("I", ('S', 22), 0, 3, 1)
82 ps
.vdd("I", ('S', 23), 0, 3, 1)
83 ps
.vss("E", ('S', 24), 0, 3, 1)
84 ps
.vdd("E", ('S', 25), 0, 3, 1)
85 ps
.uart("0", ('S', 26), 0)
86 ps
.mspi("0", ('S', 28), 0)
88 ps
.gpio("", ('E', 0), 0, 0, 6) # GPIO 0-5
89 ps
.vss("E", ('E', 6), 0, 4, 1)
90 ps
.vdd("E", ('E', 7), 0, 4, 1)
91 ps
.vdd("I", ('E', 8), 0, 4, 1)
92 ps
.vss("I", ('E', 9), 0, 4, 1)
93 ps
.gpio("", ('E', 10), 0, 6, 3) # GPIO 6-8
94 ps
.jtag("", ('E', 13), 0, 0, 4)
95 ps
.gpio("", ('E', 17), 0, 9, 5) # GPIO 9-13
96 ps
.vss("I", ('E', 22), 0, 5, 1)
97 ps
.vdd("I", ('E', 23), 0, 5, 1)
98 ps
.vss("E", ('E', 24), 0, 5, 1)
99 ps
.vdd("E", ('E', 25), 0, 5, 1)
100 ps
.gpio("", ('E', 26), 0, 14, 2) # GPIO 14-15
101 ps
.eint("", ('E', 28), 0, 0, 3)
102 ps
.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
104 ps
.vss("E", ('N', 1), 0, 6, 1)
105 ps
.vdd("E", ('N', 2), 0, 6, 1)
106 ps
.vdd("I", ('N', 3), 0, 6, 1)
107 ps
.vss("I", ('N', 4), 0, 6, 1)
108 ps
.rgmii("0", ('N', 5), 0, 0, 18)
109 #ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021)
110 #ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021)
111 #ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021)
112 ps
.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
113 ps
.vss("I", ('N', 23), 0, 7, 1)
114 ps
.vdd("I", ('N', 24), 0, 7, 1)
115 ps
.vss("E", ('N', 25), 0, 7, 1)
116 ps
.vdd("E", ('N', 26), 0, 7, 1)
118 #ps.mquadspi("1", ('S', 0), 0)
120 print ("ps clocks", ps
.clocks
)
122 # Scenarios below can be spec'd out as either "find first interface"
123 # by name/number e.g. SPI1, or as "find in bank/mux" which must be
124 # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
125 # EINT and PWM are grouped together, specially, but may still be spec'd
126 # using "BM:Name". Pins are removed in-order as listed from
127 # lists (interfaces, EINTs, PWMs) from available pins.
130 # 'SD0', litex problem 25mar2021
131 'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
134 # 'MSPI1', litex problem 25mar2021
137 ls180_pwm
= []#['B0:PWM_0']
139 'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
140 'and UART2, for debug purposes',
149 'B1:LCD/22': '18-bit RGB/TTL LCD',
150 'ULPI0/8': 'user-facing: internal (on Card), USB-OTG ULPI PHY',
151 'ULPI1': 'dual USB2 Host ULPI PHY'
154 ps
.add_scenario("Libre-SOC 2 (NGI Router) 180nm", ls180
, ls180_eint
,
155 ls180_pwm
, descriptions
)