src/spec/pinfunctions.py

   1 #!/usr/bin/env python
   2
   3 """ define functions here, with their pin names and the pin type.
   4
   5     each function returns a pair of lists
   6     (or objects with a __getitem__ function)
   7
   8     the first list (or object) contains pin name plus type specifications.
   9
  10     the type is:
  11
  12     * "-" for an input pin,
  13     * "+" for an output pin,
  14     * "*" for an in/out pin
  15
  16     each function is then added to the pinspec tuple, below, as a ("NAME",
  17     function) entry.
  18
  19     different functions may be added multiple times under the same NAME,
  20     so that complex (or large) functions can be split into one or more
  21     groups (and placed on different pinbanks).
  22
  23     eint, pwm and gpio are slightly odd in that instead of a fixed list
  24     an object is returned with a __getitem__ function that accepts a
  25     slice object.  in this way the actual generation of the pin name
  26     is delayed until it is known precisely how many pins are to be
  27     generated, and that's not known immediately (or it would be if
  28     every single one of the functions below had a start and end parameter
  29     added).  see spec.interfaces.PinGen class slice on pingroup
  30
  31     the second list is the names of pins that are part of an inout bus.
  32     this list of pins (a ganged group) will need to be changed under
  33     the control of the function, as a group.  for example: sdmmc's
  34     D0-D3 pins are in-out, they all change from input to output at
  35     the same time under the control of the function, therefore there's
  36     no point having multiple in-out switch/control wires, as the
  37     sdmmc is never going to do anything other than switch this entire
  38     bank all at once.  so in this particular example, sdmmc returns:
  39
  40         (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
  41          ['D0*', 'D1*', 'D2*', 'D3*'])                # ganged bus names
  42 """
  43
  44
  45 def i2s(suffix, bank):
  46     return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
  47             [])
  48
  49
  50 def emmc(suffix, bank, pincount=8):
  51     emmcpins = ['CMD+', 'CLK+']
  52     inout = []
  53     for i in range(pincount):
  54         pname = "D%d*" % i
  55         emmcpins.append(pname)
  56         inout.append(pname)
  57     return (emmcpins, inout)
  58
  59
  60 def sdmmc(suffix, bank):
  61     return emmc(suffix, bank, pincount=4)
  62
  63
  64 def nspi(suffix, bank, iosize, masteronly=True):
  65     if masteronly:
  66         qpins = ['CK+', 'NSS+']
  67     else:
  68         qpins = ['CK*', 'NSS*']
  69     inout = []
  70     for i in range(iosize):
  71         pname = "IO%d*" % i
  72         qpins.append(pname)
  73         inout.append(pname)
  74     return (qpins, inout)
  75
  76
  77 def mspi(suffix, bank):
  78     return nspi(suffix, bank, 2, masteronly=True)
  79
  80
  81 def mquadspi(suffix, bank):
  82     return nspi(suffix, bank, 4, masteronly=True)
  83
  84
  85 def spi(suffix, bank):
  86     return nspi(suffix, bank, 2)
  87
  88
  89 def quadspi(suffix, bank):
  90     return nspi(suffix, bank, 4)
  91
  92
  93 def i2c(suffix, bank):
  94     return (['SDA*', 'SCL*'], [])
  95
  96
  97 def jtag(suffix, bank):
  98     return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
  99
 100
 101 def uart(suffix, bank):
 102     return (['TX+', 'RX-'], [])
 103
 104
 105 def ulpi(suffix, bank):
 106     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 107     for i in range(8):
 108         ulpipins.append('D%d*' % i)
 109     return (ulpipins, [])
 110
 111
 112 def uartfull(suffix, bank):
 113     return (['TX+', 'RX-', 'CTS-', 'RTS+'],
 114             [])
 115
 116
 117 def rgbttl(suffix, bank):
 118     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 119     for i in range(24):
 120         ttlpins.append("OUT%d+" % i)
 121     return (ttlpins, [])
 122
 123
 124 def rgmii(suffix, bank):
 125     buspins = []
 126     for i in range(4):
 127         buspins.append("ERXD%d-" % i)
 128     for i in range(4):
 129         buspins.append("ETXD%d+" % i)
 130     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 131                 'EMDC+', 'EMDIO*',
 132                 'ETXEN+', 'ETXCK+', 'ECRS-',
 133                 'ECOL+', 'ETXERR+']
 134     return (buspins, [])
 135
 136
 137 def flexbus1(suffix, bank):
 138     buspins = []
 139     inout = []
 140     for i in range(8):
 141         pname = "AD%d*" % i
 142         buspins.append(pname)
 143         inout.append(pname)
 144     for i in range(2):
 145         buspins.append("CS%d+" % i)
 146     buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
 147                 # 'TS+',  commented out for now, mirrors ALE, for mux'd mode
 148                 'TBST+',
 149                 'TSIZ0+', 'TSIZ1+']
 150     for i in range(4):
 151         buspins.append("BWE%d+" % i)
 152     for i in range(2, 6):
 153         buspins.append("CS%d+" % i)
 154     return (buspins, inout)
 155
 156
 157 def flexbus2(suffix, bank):
 158     buspins = []
 159     for i in range(8, 32):
 160         buspins.append("AD%d*" % i)
 161     return (buspins, buspins)
 162
 163
 164 def sdram1(suffix, bank):
 165     buspins = []
 166     inout = []
 167     for i in range(8):
 168         pname = "SDRDQM%d*" % i
 169         buspins.append(pname)
 170     for i in range(8):
 171         pname = "SDRD%d*" % i
 172         buspins.append(pname)
 173         inout.append(pname)
 174     for i in range(12):
 175         buspins.append("SDRAD%d+" % i)
 176     for i in range(8):
 177         buspins.append("SDRDEN%d+" % i)
 178     for i in range(2):
 179         buspins.append("SDRBA%d+" % i)
 180     buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
 181                 'SDRCSn0++']
 182     return (buspins, inout)
 183
 184
 185 def sdram2(suffix, bank):
 186     buspins = []
 187     inout = []
 188     for i in range(1, 6):
 189         buspins.append("SDRCSn%d+" % i)
 190     for i in range(8, 16):
 191         pname = "SDRDQM%d*" % i
 192         buspins.append(pname)
 193     for i in range(8, 16):
 194         pname = "SDRD%d*" % i
 195         buspins.append(pname)
 196         inout.append(pname)
 197     return (buspins, inout)
 198
 199
 200 def sdram3(suffix, bank):
 201     buspins = []
 202     inout = []
 203     for i in range(12, 13):
 204         buspins.append("SDRAD%d+" % i)
 205     for i in range(8, 64):
 206         pname = "SDRD%d*" % i
 207         buspins.append(pname)
 208         inout.append(pname)
 209     return (buspins, inout)
 210
 211
 212 def mcu8080(suffix, bank):
 213     buspins = []
 214     inout = []
 215     for i in range(8):
 216         pname = "MCUD%d*" % i
 217         buspins.append(pname)
 218         inout.append(pname)
 219     for i in range(8):
 220         buspins.append("MCUAD%d+" % (i + 8))
 221     for i in range(6):
 222         buspins.append("MCUCS%d+" % i)
 223     for i in range(2):
 224         buspins.append("MCUNRB%d+" % i)
 225     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 226                 'MCURST+']
 227     return (buspins, inout)
 228
 229
 230 class RangePin(object):
 231     def __init__(self, suffix, prefix=None):
 232         self.suffix = suffix
 233         self.prefix = prefix or ''
 234
 235     def __getitem__(self, s):
 236         res = []
 237         for idx in range(s.start or 0, s.stop or -1, s.step or 1):
 238             res.append("%s%d%s" % (self.prefix, idx, self.suffix))
 239         return res
 240
 241
 242 def eint(suffix, bank):
 243     return (RangePin("-"), [])
 244
 245
 246 def pwm(suffix, bank):
 247     return (RangePin("+"), [])
 248
 249
 250 def gpio(suffix, bank):
 251     return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [])
 252
 253
 254 # list functions by name here
 255
 256 pinspec = (('IIS', i2s),
 257            ('MMC', emmc),
 258            ('SD', sdmmc),
 259            ('MSPI', mspi),
 260            ('MQSPI', mquadspi),
 261            ('SPI', spi),
 262            ('QSPI', quadspi),
 263            ('TWI', i2c),
 264            ('JTAG', jtag),
 265            ('UART', uart),
 266            ('QUART', uartfull),
 267            ('LCD', rgbttl),
 268            ('ULPI', ulpi),
 269            ('RG', rgmii),
 270            ('FB', flexbus1),
 271            ('FB', flexbus2),
 272            ('SDR', sdram1),
 273            ('SDR', sdram2),
 274            ('SDR', sdram3),
 275            ('EINT', eint),
 276            ('PWM', pwm),
 277            ('GPIO', gpio),
 278            )