src/spec/pinfunctions.py

   1 #!/usr/bin/env python
   2
   3 """ define functions here, with their pin names and the pin type.
   4
   5     each function returns a pair of lists
   6     (or objects with a __getitem__ function)
   7
   8     the first list (or object) contains pin name plus type specifications.
   9
  10     the type is:
  11
  12     * "-" for an input pin,
  13     * "+" for an output pin,
  14     * "*" for an in/out pin
  15
  16     each function is then added to the pinspec tuple, below, as a ("NAME",
  17     function) entry.
  18
  19     different functions may be added multiple times under the same NAME,
  20     so that complex (or large) functions can be split into one or more
  21     groups (and placed on different pinbanks).
  22
  23     eint, pwm and gpio are slightly odd in that instead of a fixed list
  24     an object is returned with a __getitem__ function that accepts a
  25     slice object.  in this way the actual generation of the pin name
  26     is delayed until it is known precisely how many pins are to be
  27     generated, and that's not known immediately (or it would be if
  28     every single one of the functions below had a start and end parameter
  29     added).  see spec.interfaces.PinGen class slice on pingroup
  30
  31     the second list is the names of pins that are part of an inout bus.
  32     this list of pins (a ganged group) will need to be changed under
  33     the control of the function, as a group.  for example: sdmmc's
  34     D0-D3 pins are in-out, they all change from input to output at
  35     the same time under the control of the function, therefore there's
  36     no point having multiple in-out switch/control wires, as the
  37     sdmmc is never going to do anything other than switch this entire
  38     bank all at once.  so in this particular example, sdmmc returns:
  39
  40         (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
  41          ['D0*', 'D1*', 'D2*', 'D3*'])                # ganged bus names
  42 """
  43
  44
  45 def i2s(suffix, bank):
  46     return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
  47             [])
  48
  49
  50 def emmc(suffix, bank, pincount=8):
  51     emmcpins = ['CMD+', 'CLK+']
  52     inout = []
  53     for i in range(pincount):
  54         pname = "D%d*" % i
  55         emmcpins.append(pname)
  56         inout.append(pname)
  57     return (emmcpins, inout)
  58
  59
  60 def sdmmc(suffix, bank):
  61     return emmc(suffix, bank, pincount=4)
  62
  63
  64 def nspi(suffix, bank, iosize, masteronly=True):
  65     if masteronly:
  66         qpins = ['CK+', 'NSS+']
  67     else:
  68         qpins = ['CK*', 'NSS*']
  69     inout = []
  70     for i in range(iosize):
  71         pname = "IO%d*" % i
  72         qpins.append(pname)
  73         inout.append(pname)
  74     return (qpins, inout)
  75
  76 def mspi(suffix, bank):
  77     return nspi(suffix, bank, 2, masteronly=True)
  78
  79
  80 def mquadspi(suffix, bank):
  81     return nspi(suffix, bank, 4, masteronly=True)
  82
  83
  84 def spi(suffix, bank):
  85     return nspi(suffix, bank, 2)
  86
  87
  88 def quadspi(suffix, bank):
  89     return nspi(suffix, bank, 4)
  90
  91
  92 def i2c(suffix, bank):
  93     return (['SDA*', 'SCL*'], [])
  94
  95
  96 def jtag(suffix, bank):
  97     return (['TMS+', 'TDI-', 'TDO+', 'TCK+'], [])
  98
  99
 100 def uart(suffix, bank):
 101     return (['TX+', 'RX-'], [])
 102
 103
 104 def ulpi(suffix, bank):
 105     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 106     for i in range(8):
 107         ulpipins.append('D%d*' % i)
 108     return (ulpipins, [])
 109
 110
 111 def uartfull(suffix, bank):
 112     return (['TX+', 'RX-', 'CTS-', 'RTS+'],
 113             [])
 114
 115
 116 def rgbttl(suffix, bank):
 117     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 118     for i in range(24):
 119         ttlpins.append("OUT%d+" % i)
 120     return (ttlpins, [])
 121
 122
 123 def rgmii(suffix, bank):
 124     buspins = []
 125     for i in range(4):
 126         buspins.append("ERXD%d-" % i)
 127     for i in range(4):
 128         buspins.append("ETXD%d+" % i)
 129     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 130                 'EMDC+', 'EMDIO*',
 131                 'ETXEN+', 'ETXCK+', 'ECRS-',
 132                 'ECOL+', 'ETXERR+']
 133     return (buspins, [])
 134
 135
 136 def flexbus1(suffix, bank):
 137     buspins = []
 138     inout = []
 139     for i in range(8):
 140         pname = "AD%d*" % i
 141         buspins.append(pname)
 142         inout.append(pname)
 143     for i in range(2):
 144         buspins.append("CS%d+" % i)
 145     buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
 146                 'A0', 'A1', 'TS', 'TBST',
 147                 'TSIZ0', 'TSIZ1']
 148     for i in range(4):
 149         buspins.append("BWE%d" % i)
 150     for i in range(2, 6):
 151         buspins.append("CS%d+" % i)
 152     return (buspins, inout)
 153
 154
 155 def flexbus2(suffix, bank):
 156     buspins = []
 157     for i in range(8, 32):
 158         buspins.append("AD%d*" % i)
 159     return (buspins, buspins)
 160
 161
 162 def sdram1(suffix, bank):
 163     buspins = []
 164     inout = []
 165     for i in range(16):
 166         pname = "SDRDQM%d*" % i
 167         buspins.append(pname)
 168         inout.append(pname)
 169     for i in range(12):
 170         buspins.append("SDRAD%d+" % i)
 171     for i in range(8):
 172         buspins.append("SDRDQ%d+" % i)
 173     for i in range(3):
 174         buspins.append("SDRCS%d#+" % i)
 175     for i in range(2):
 176         buspins.append("SDRDQ%d+" % i)
 177     for i in range(2):
 178         buspins.append("SDRBA%d+" % i)
 179     buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
 180                 'SDRRST+']
 181     return (buspins, inout)
 182
 183
 184 def sdram2(suffix, bank):
 185     buspins = []
 186     inout = []
 187     for i in range(3, 6):
 188         buspins.append("SDRCS%d#+" % i)
 189     for i in range(16, 32):
 190         pname = "SDRDQM%d*" % i
 191         buspins.append(pname)
 192         inout.append(pname)
 193     return (buspins, inout)
 194
 195
 196 def mcu8080(suffix, bank):
 197     buspins = []
 198     inout = []
 199     for i in range(8):
 200         pname = "MCUD%d*" % i
 201         buspins.append(pname)
 202         inout.append(pname)
 203     for i in range(8):
 204         buspins.append("MCUAD%d+" % (i + 8))
 205     for i in range(6):
 206         buspins.append("MCUCS%d+" % i)
 207     for i in range(2):
 208         buspins.append("MCUNRB%d+" % i)
 209     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 210                 'MCURST+']
 211     return (buspins, inout)
 212
 213
 214 class RangePin(object):
 215     def __init__(self, suffix, prefix=None):
 216         self.suffix = suffix
 217         self.prefix = prefix or ''
 218
 219     def __getitem__(self, s):
 220         res = []
 221         for idx in range(s.start or 0, s.stop or -1, s.step or 1):
 222             res.append("%s%d%s" % (self.prefix, idx, self.suffix))
 223         return res
 224
 225
 226 def eint(suffix, bank):
 227     return (RangePin("-"), [])
 228
 229
 230 def pwm(suffix, bank):
 231     return (RangePin("+"), [])
 232
 233
 234 def gpio(suffix, bank):
 235     return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [])
 236
 237
 238 # list functions by name here
 239
 240 pinspec = (('IIS', i2s),
 241            ('MMC', emmc),
 242            ('SD', sdmmc),
 243            ('MSPI', mspi),
 244            ('MQSPI', mquadspi),
 245            ('SPI', spi),
 246            ('QSPI', quadspi),
 247            ('TWI', i2c),
 248            ('JTAG', jtag),
 249            ('UART', uart),
 250            ('QUART', uartfull),
 251            ('LCD', rgbttl),
 252            ('ULPI', ulpi),
 253            ('RG', rgmii),
 254            ('FB', flexbus1),
 255            ('FB', flexbus2),
 256            ('SDR', sdram1),
 257            ('SDR', sdram2),
 258            ('EINT', eint),
 259            ('PWM', pwm),
 260            ('GPIO', gpio),
 261            )