src/spec/pinfunctions.py

   1 #!/usr/bin/env python
   2
   3 """ define functions here, with their pin names and the pin type.
   4
   5     each function returns a pair of lists
   6     (or objects with a __getitem__ function)
   7
   8     the first list (or object) contains pin name plus type specifications.
   9
  10     the type is:
  11
  12     * "-" for an input pin,
  13     * "+" for an output pin,
  14     * "*" for an in/out pin
  15
  16     each function is then added to the pinspec tuple, below, as a ("NAME",
  17     function) entry.
  18
  19     different functions may be added multiple times under the same NAME,
  20     so that complex (or large) functions can be split into one or more
  21     groups (and placed on different pinbanks).
  22
  23     eint, pwm and gpio are slightly odd in that instead of a fixed list
  24     an object is returned with a __getitem__ function that accepts a
  25     slice object.  in this way the actual generation of the pin name
  26     is delayed until it is known precisely how many pins are to be
  27     generated, and that's not known immediately (or it would be if
  28     every single one of the functions below had a start and end parameter
  29     added).  see spec.interfaces.PinGen class slice on pingroup
  30
  31     the second list is the names of pins that are part of an inout bus.
  32     this list of pins (a ganged group) will need to be changed under
  33     the control of the function, as a group.  for example: sdmmc's
  34     D0-D3 pins are in-out, they all change from input to output at
  35     the same time under the control of the function, therefore there's
  36     no point having multiple in-out switch/control wires, as the
  37     sdmmc is never going to do anything other than switch this entire
  38     bank all at once.  so in this particular example, sdmmc returns:
  39
  40         (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
  41          ['D0*', 'D1*', 'D2*', 'D3*'])                # ganged bus names
  42 """
  43
  44
  45 def i2s(suffix, bank):
  46     return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
  47             [])
  48
  49
  50 def emmc(suffix, bank, pincount=8):
  51     emmcpins = ['CMD+', 'CLK+']
  52     inout = []
  53     for i in range(pincount):
  54         pname = "D%d*" % i
  55         emmcpins.append(pname)
  56         inout.append(pname)
  57     return (emmcpins, inout)
  58
  59
  60 def sdmmc(suffix, bank):
  61     return emmc(suffix, bank, pincount=4)
  62
  63
  64 def nspi(suffix, bank, iosize):
  65     qpins = ['CK*', 'NSS*']
  66     inout = []
  67     for i in range(iosize):
  68         pname = "IO%d*" % i
  69         qpins.append(pname)
  70         inout.append(pname)
  71     return (qpins, inout)
  72
  73 def spi(suffix, bank):
  74     return nspi(suffix, bank, 2)
  75
  76
  77 def quadspi(suffix, bank):
  78     return nspi(suffix, bank, 4)
  79
  80
  81 def i2c(suffix, bank):
  82     return (['SDA*', 'SCL*'], [])
  83
  84
  85 def jtag(suffix, bank):
  86     return (['TMS+', 'TDI-', 'TDO+', 'TCK+'], [])
  87
  88
  89 def uart(suffix, bank):
  90     return (['TX+', 'RX-'], [])
  91
  92
  93 def ulpi(suffix, bank):
  94     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
  95     for i in range(8):
  96         ulpipins.append('D%d*' % i)
  97     return (ulpipins, [])
  98
  99
 100 def uartfull(suffix, bank):
 101     return (['TX+', 'RX-', 'CTS-', 'RTS+'],
 102             [])
 103
 104
 105 def rgbttl(suffix, bank):
 106     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 107     for i in range(24):
 108         ttlpins.append("OUT%d+" % i)
 109     return (ttlpins, [])
 110
 111
 112 def rgmii(suffix, bank):
 113     buspins = []
 114     for i in range(4):
 115         buspins.append("ERXD%d-" % i)
 116     for i in range(4):
 117         buspins.append("ETXD%d+" % i)
 118     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 119                 'EMDC+', 'EMDIO*',
 120                 'ETXEN+', 'ETXCK+', 'ECRS-',
 121                 'ECOL+', 'ETXERR+']
 122     return (buspins, [])
 123
 124
 125 def flexbus1(suffix, bank):
 126     buspins = []
 127     inout = []
 128     for i in range(8):
 129         pname = "AD%d*" % i
 130         buspins.append(pname)
 131         inout.append(pname)
 132     for i in range(2):
 133         buspins.append("CS%d+" % i)
 134     buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
 135                 'A0', 'A1', 'TS', 'TBST',
 136                 'TSIZ0', 'TSIZ1']
 137     for i in range(4):
 138         buspins.append("BWE%d" % i)
 139     for i in range(2, 6):
 140         buspins.append("CS%d+" % i)
 141     return (buspins, inout)
 142
 143
 144 def flexbus2(suffix, bank):
 145     buspins = []
 146     for i in range(8, 32):
 147         buspins.append("AD%d*" % i)
 148     return (buspins, buspins)
 149
 150
 151 def sdram1(suffix, bank):
 152     buspins = []
 153     inout = []
 154     for i in range(16):
 155         pname = "SDRDQM%d*" % i
 156         buspins.append(pname)
 157         inout.append(pname)
 158     for i in range(12):
 159         buspins.append("SDRAD%d+" % i)
 160     for i in range(8):
 161         buspins.append("SDRDQ%d+" % i)
 162     for i in range(3):
 163         buspins.append("SDRCS%d#+" % i)
 164     for i in range(2):
 165         buspins.append("SDRDQ%d+" % i)
 166     for i in range(2):
 167         buspins.append("SDRBA%d+" % i)
 168     buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
 169                 'SDRRST+']
 170     return (buspins, inout)
 171
 172
 173 def sdram2(suffix, bank):
 174     buspins = []
 175     inout = []
 176     for i in range(3, 6):
 177         buspins.append("SDRCS%d#+" % i)
 178     for i in range(16, 32):
 179         pname = "SDRDQM%d*" % i
 180         buspins.append(pname)
 181         inout.append(pname)
 182     return (buspins, inout)
 183
 184
 185 def mcu8080(suffix, bank):
 186     buspins = []
 187     inout = []
 188     for i in range(8):
 189         pname = "MCUD%d*" % i
 190         buspins.append(pname)
 191         inout.append(pname)
 192     for i in range(8):
 193         buspins.append("MCUAD%d+" % (i + 8))
 194     for i in range(6):
 195         buspins.append("MCUCS%d+" % i)
 196     for i in range(2):
 197         buspins.append("MCUNRB%d+" % i)
 198     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 199                 'MCURST+']
 200     return (buspins, inout)
 201
 202
 203 class RangePin(object):
 204     def __init__(self, suffix, prefix=None):
 205         self.suffix = suffix
 206         self.prefix = prefix or ''
 207
 208     def __getitem__(self, s):
 209         res = []
 210         for idx in range(s.start or 0, s.stop or -1, s.step or 1):
 211             res.append("%s%d%s" % (self.prefix, idx, self.suffix))
 212         return res
 213
 214
 215 def eint(suffix, bank):
 216     return (RangePin("-"), [])
 217
 218
 219 def pwm(suffix, bank):
 220     return (RangePin("+"), [])
 221
 222
 223 def gpio(suffix, bank):
 224     return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [])
 225
 226
 227 # list functions by name here
 228
 229 pinspec = (('IIS', i2s),
 230            ('MMC', emmc),
 231            ('SD', sdmmc),
 232            ('SPI', spi),
 233            ('QSPI', quadspi),
 234            ('TWI', i2c),
 235            ('JTAG', jtag),
 236            ('UART', uart),
 237            ('QUART', uartfull),
 238            ('LCD', rgbttl),
 239            ('ULPI', ulpi),
 240            ('RG', rgmii),
 241            ('FB', flexbus1),
 242            ('FB', flexbus2),
 243            ('SDR', sdram1),
 244            ('SDR', sdram2),
 245            ('EINT', eint),
 246            ('PWM', pwm),
 247            ('GPIO', gpio),
 248            )