src/spec/pinfunctions.py

   1 #!/usr/bin/env python
   2
   3 """ define functions here, with their pin names and the pin type.
   4
   5     each function returns a pair of lists
   6     (or objects with a __getitem__ function)
   7
   8     the first list (or object) contains pin name plus type specifications.
   9
  10     the type is:
  11
  12     * "-" for an input pin,
  13     * "+" for an output pin,
  14     * "*" for an in/out pin
  15
  16     each function is then added to the pinspec tuple, below, as a ("NAME",
  17     function) entry.
  18
  19     different functions may be added multiple times under the same NAME,
  20     so that complex (or large) functions can be split into one or more
  21     groups (and placed on different pinbanks).
  22
  23     eint, pwm and gpio are slightly odd in that instead of a fixed list
  24     an object is returned with a __getitem__ function that accepts a
  25     slice object.  in this way the actual generation of the pin name
  26     is delayed until it is known precisely how many pins are to be
  27     generated, and that's not known immediately (or it would be if
  28     every single one of the functions below had a start and end parameter
  29     added).  see spec.interfaces.PinGen class slice on pingroup
  30
  31     the second list is the names of pins that are part of an inout bus.
  32     this list of pins (a ganged group) will need to be changed under
  33     the control of the function, as a group.  for example: sdmmc's
  34     D0-D3 pins are in-out, they all change from input to output at
  35     the same time under the control of the function, therefore there's
  36     no point having multiple in-out switch/control wires, as the
  37     sdmmc is never going to do anything other than switch this entire
  38     bank all at once.  so in this particular example, sdmmc returns:
  39
  40         (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
  41          ['D0*', 'D1*', 'D2*', 'D3*'])                # ganged bus names
  42 """
  43
  44
  45 def i2s(suffix, bank):
  46     return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
  47             [])
  48
  49
  50 def emmc(suffix, bank, pincount=8):
  51     emmcpins = ['CMD+', 'CLK+']
  52     inout = []
  53     for i in range(pincount):
  54         pname = "D%d*" % i
  55         emmcpins.append(pname)
  56         inout.append(pname)
  57     return (emmcpins, inout)
  58
  59
  60 def sdmmc(suffix, bank):
  61     return emmc(suffix, bank, pincount=4)
  62
  63
  64 def nspi(suffix, bank, iosize, masteronly=True):
  65     if masteronly:
  66         qpins = ['CK+', 'NSS+']
  67     else:
  68         qpins = ['CK*', 'NSS*']
  69     inout = []
  70     for i in range(iosize):
  71         pname = "IO%d*" % i
  72         qpins.append(pname)
  73         inout.append(pname)
  74     return (qpins, inout)
  75
  76
  77 def mspi(suffix, bank):
  78     return nspi(suffix, bank, 2, masteronly=True)
  79
  80
  81 def mquadspi(suffix, bank):
  82     return nspi(suffix, bank, 4, masteronly=True)
  83
  84
  85 def spi(suffix, bank):
  86     return nspi(suffix, bank, 2)
  87
  88
  89 def quadspi(suffix, bank):
  90     return nspi(suffix, bank, 4)
  91
  92
  93 def i2c(suffix, bank):
  94     return (['SDA*', 'SCL*'], [])
  95
  96
  97 def jtag(suffix, bank):
  98     return (['TMS+', 'TDI-', 'TDO+', 'TCK+'], [])
  99
 100
 101 def uart(suffix, bank):
 102     return (['TX+', 'RX-'], [])
 103
 104
 105 def ulpi(suffix, bank):
 106     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 107     for i in range(8):
 108         ulpipins.append('D%d*' % i)
 109     return (ulpipins, [])
 110
 111
 112 def uartfull(suffix, bank):
 113     return (['TX+', 'RX-', 'CTS-', 'RTS+'],
 114             [])
 115
 116
 117 def rgbttl(suffix, bank):
 118     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 119     for i in range(24):
 120         ttlpins.append("OUT%d+" % i)
 121     return (ttlpins, [])
 122
 123
 124 def rgmii(suffix, bank):
 125     buspins = []
 126     for i in range(4):
 127         buspins.append("ERXD%d-" % i)
 128     for i in range(4):
 129         buspins.append("ETXD%d+" % i)
 130     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 131                 'EMDC+', 'EMDIO*',
 132                 'ETXEN+', 'ETXCK+', 'ECRS-',
 133                 'ECOL+', 'ETXERR+']
 134     return (buspins, [])
 135
 136
 137 def flexbus1(suffix, bank):
 138     buspins = []
 139     inout = []
 140     for i in range(8):
 141         pname = "AD%d*" % i
 142         buspins.append(pname)
 143         inout.append(pname)
 144     for i in range(2):
 145         buspins.append("CS%d+" % i)
 146     buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
 147                 'A0', 'A1', 'TS', 'TBST',
 148                 'TSIZ0', 'TSIZ1']
 149     for i in range(4):
 150         buspins.append("BWE%d" % i)
 151     for i in range(2, 6):
 152         buspins.append("CS%d+" % i)
 153     return (buspins, inout)
 154
 155
 156 def flexbus2(suffix, bank):
 157     buspins = []
 158     for i in range(8, 32):
 159         buspins.append("AD%d*" % i)
 160     return (buspins, buspins)
 161
 162
 163 def sdram1(suffix, bank):
 164     buspins = []
 165     inout = []
 166     for i in range(16):
 167         pname = "SDRDQM%d*" % i
 168         buspins.append(pname)
 169         inout.append(pname)
 170     for i in range(12):
 171         buspins.append("SDRAD%d+" % i)
 172     for i in range(8):
 173         buspins.append("SDRDQ%d+" % i)
 174     for i in range(3):
 175         buspins.append("SDRCS%d#+" % i)
 176     for i in range(2):
 177         buspins.append("SDRDQ%d+" % i)
 178     for i in range(2):
 179         buspins.append("SDRBA%d+" % i)
 180     buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
 181                 'SDRRST+']
 182     return (buspins, inout)
 183
 184
 185 def sdram2(suffix, bank):
 186     buspins = []
 187     inout = []
 188     for i in range(3, 6):
 189         buspins.append("SDRCS%d#+" % i)
 190     for i in range(16, 32):
 191         pname = "SDRDQM%d*" % i
 192         buspins.append(pname)
 193         inout.append(pname)
 194     return (buspins, inout)
 195
 196
 197 def mcu8080(suffix, bank):
 198     buspins = []
 199     inout = []
 200     for i in range(8):
 201         pname = "MCUD%d*" % i
 202         buspins.append(pname)
 203         inout.append(pname)
 204     for i in range(8):
 205         buspins.append("MCUAD%d+" % (i + 8))
 206     for i in range(6):
 207         buspins.append("MCUCS%d+" % i)
 208     for i in range(2):
 209         buspins.append("MCUNRB%d+" % i)
 210     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 211                 'MCURST+']
 212     return (buspins, inout)
 213
 214
 215 class RangePin(object):
 216     def __init__(self, suffix, prefix=None):
 217         self.suffix = suffix
 218         self.prefix = prefix or ''
 219
 220     def __getitem__(self, s):
 221         res = []
 222         for idx in range(s.start or 0, s.stop or -1, s.step or 1):
 223             res.append("%s%d%s" % (self.prefix, idx, self.suffix))
 224         return res
 225
 226
 227 def eint(suffix, bank):
 228     return (RangePin("-"), [])
 229
 230
 231 def pwm(suffix, bank):
 232     return (RangePin("+"), [])
 233
 234
 235 def gpio(suffix, bank):
 236     return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [])
 237
 238
 239 # list functions by name here
 240
 241 pinspec = (('IIS', i2s),
 242            ('MMC', emmc),
 243            ('SD', sdmmc),
 244            ('MSPI', mspi),
 245            ('MQSPI', mquadspi),
 246            ('SPI', spi),
 247            ('QSPI', quadspi),
 248            ('TWI', i2c),
 249            ('JTAG', jtag),
 250            ('UART', uart),
 251            ('QUART', uartfull),
 252            ('LCD', rgbttl),
 253            ('ULPI', ulpi),
 254            ('RG', rgmii),
 255            ('FB', flexbus1),
 256            ('FB', flexbus2),
 257            ('SDR', sdram1),
 258            ('SDR', sdram2),
 259            ('EINT', eint),
 260            ('PWM', pwm),
 261            ('GPIO', gpio),
 262            )