return which pins are inout-buses from spec pinfunctions
[pinmux.git] / src / spec / pinfunctions.py
1 #!/usr/bin/env python
2
3 """ define functions here, with their pin names and the pin type.
4
5 each function returns a list (or an object with a __getitem__ function)
6 containing pin name plus type specifications.
7
8 the type is:
9
10 * "-" for an input pin,
11 * "+" for an output pin,
12 * "*" for an in/out pin
13
14 each function is then added to the pinspec tuple, below, as a ("NAME",
15 function) entry.
16
17 different functions may be added multiple times under the same NAME,
18 so that complex (or large) functions can be split into one or more
19 groups (and placed on different pinbanks).
20
21 eint, pwm and gpio are slightly odd in that instead of a fixed list
22 an object is returned with a __getitem__ function that accepts a
23 slice object. in this way the actual generation of the pin name
24 is delayed until it is known precisely how many pins are to be
25 generated, and that's not known immediately (or it would be if
26 every single one of the functions below had a start and end parameter
27 added). see spec.interfaces.PinGen class slice on pingroup
28 """
29
30
31 def i2s(suffix, bank):
32 return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
33 [])
34
35
36 def emmc(suffix, bank, pincount=8):
37 emmcpins = ['CMD+', 'CLK+']
38 inout = []
39 for i in range(pincount):
40 pname = "D%d*" % i
41 emmcpins.append(pname)
42 inout.append(pname)
43 return (emmcpins, inout)
44
45
46 def sdmmc(suffix, bank):
47 return emmc(suffix, bank, pincount=4)
48
49
50 def spi(suffix, bank):
51 pins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
52 return (pins, [])
53
54
55 def quadspi(suffix, bank):
56 qpins = ['CK*', 'NSS*']
57 inout = []
58 for i in range(4):
59 pname = "IO%d*" % i
60 qpins.append(pname)
61 inout.append(pname)
62 return (qpins, inout)
63
64
65 def i2c(suffix, bank):
66 return (['SDA*', 'SCL*'], [])
67
68
69 def jtag(suffix, bank):
70 return (['MS+', 'DI-', 'DO+', 'CK+'], [])
71
72
73 def uart(suffix, bank):
74 return (['TX+', 'RX-'], [])
75
76
77 def ulpi(suffix, bank):
78 ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
79 for i in range(8):
80 ulpipins.append('D%d*' % i)
81 return (ulpipins, [])
82
83
84 def uartfull(suffix, bank):
85 return (['TX+', 'RX-', 'CTS-', 'RTS+'],
86 [])
87
88
89 def rgbttl(suffix, bank):
90 ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
91 for i in range(24):
92 ttlpins.append("D%d+" % i)
93 return (ttlpins, [])
94
95
96 def rgmii(suffix, bank):
97 buspins = []
98 for i in range(4):
99 buspins.append("ERXD%d-" % i)
100 for i in range(4):
101 buspins.append("ETXD%d+" % i)
102 buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
103 'EMDC+', 'EMDIO*',
104 'ETXEN+', 'ETXCK+', 'ECRS-',
105 'ECOL+', 'ETXERR+']
106 return (buspins, [])
107
108
109 def flexbus1(suffix, bank):
110 buspins = []
111 inout = []
112 for i in range(8):
113 pname = "AD%d*" % i
114 buspins.append(pname)
115 inout.append(pname)
116 for i in range(2):
117 buspins.append("CS%d+" % i)
118 buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
119 'A0', 'A1', 'TS', 'TBST',
120 'TSIZ0', 'TSIZ1']
121 for i in range(4):
122 buspins.append("BWE%d" % i)
123 for i in range(2, 6):
124 buspins.append("CS%d+" % i)
125 return (buspins, inout)
126
127
128 def flexbus2(suffix, bank):
129 buspins = []
130 for i in range(8, 32):
131 buspins.append("AD%d*" % i)
132 return (buspins, buspins)
133
134
135 def sdram1(suffix, bank):
136 buspins = []
137 inout = []
138 for i in range(16):
139 pname = "SDRDQM%d*" % i
140 buspins.append(pname)
141 inout.append(pname)
142 for i in range(12):
143 buspins.append("SDRAD%d+" % i)
144 for i in range(8):
145 buspins.append("SDRDQ%d+" % i)
146 for i in range(3):
147 buspins.append("SDRCS%d#+" % i)
148 for i in range(2):
149 buspins.append("SDRDQ%d+" % i)
150 for i in range(2):
151 buspins.append("SDRBA%d+" % i)
152 buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
153 'SDRRST+']
154 return (buspins, inout)
155
156
157 def sdram2(suffix, bank):
158 buspins = []
159 inout = []
160 for i in range(3, 6):
161 buspins.append("SDRCS%d#+" % i)
162 for i in range(16, 32):
163 pname = "SDRDQM%d*" % i
164 buspins.append(pname)
165 inout.append(pname)
166 return (buspins, inout)
167
168
169 def mcu8080(suffix, bank):
170 buspins = []
171 inout = []
172 for i in range(8):
173 pname = "MCUD%d*" % i
174 buspins.append(pname)
175 inout.append(pname)
176 for i in range(8):
177 buspins.append("MCUAD%d+" % (i + 8))
178 for i in range(6):
179 buspins.append("MCUCS%d+" % i)
180 for i in range(2):
181 buspins.append("MCUNRB%d+" % i)
182 buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
183 'MCURST+']
184 return (buspins, inout)
185
186
187 class RangePin(object):
188 def __init__(self, suffix, prefix=None):
189 self.suffix = suffix
190 self.prefix = prefix or ''
191
192 def __getitem__(self, s):
193 res = []
194 for idx in range(s.start or 0, s.stop or -1, s.step or 1):
195 res.append("%s%d%s" % (self.prefix, idx, self.suffix))
196 return res
197
198
199 def eint(suffix, bank):
200 return (RangePin("*"), [])
201
202
203 def pwm(suffix, bank):
204 return (RangePin("+"), [])
205
206
207 def gpio(suffix, bank):
208 return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [])
209
210
211 # list functions by name here
212
213 pinspec = (('IIS', i2s),
214 ('MMC', emmc),
215 ('SD', sdmmc),
216 ('SPI', spi),
217 ('QSPI', quadspi),
218 ('TWI', i2c),
219 ('JTAG', jtag),
220 ('UART', uart),
221 ('UARTQ', uartfull),
222 ('LCD', rgbttl),
223 ('ULPI', ulpi),
224 ('RG', rgmii),
225 ('FB', flexbus1),
226 ('FB', flexbus2),
227 ('SDR', sdram1),
228 ('SDR', sdram2),
229 ('EINT', eint),
230 ('PWM', pwm),
231 ('GPIO', gpio),
232 )