3 """ define functions here, with their pin names and the pin type.
5 each function returns a list (or an object with a __getitem__ function)
6 containing pin name plus type specifications.
10 * "-" for an input pin,
11 * "+" for an output pin,
12 * "*" for an in/out pin
14 each function is then added to the pinspec tuple, below, as a ("NAME",
17 different functions may be added multiple times under the same NAME,
18 so that complex (or large) functions can be split into one or more
19 groups (and placed on different pinbanks).
21 eint, pwm and gpio are slightly odd in that instead of a fixed list
22 an object is returned with a __getitem__ function that accepts a
23 slice object. in this way the actual generation of the pin name
24 is delayed until it is known precisely how many pins are to be
25 generated, and that's not known immediately (or it would be if
26 every single one of the functions below had a start and end parameter
27 added). see spec.interfaces.PinGen class slice on pingroup
31 def i2s(suffix
, bank
):
32 return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
36 def emmc(suffix
, bank
, pincount
=8):
37 emmcpins
= ['CMD+', 'CLK+']
39 for i
in range(pincount
):
41 emmcpins
.append(pname
)
43 return (emmcpins
, inout
)
46 def sdmmc(suffix
, bank
):
47 return emmc(suffix
, bank
, pincount
=4)
50 def spi(suffix
, bank
):
51 pins
= ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
55 def quadspi(suffix
, bank
):
56 qpins
= ['CK*', 'NSS*']
65 def i2c(suffix
, bank
):
66 return (['SDA*', 'SCL*'], [])
69 def jtag(suffix
, bank
):
70 return (['MS+', 'DI-', 'DO+', 'CK+'], [])
73 def uart(suffix
, bank
):
74 return (['TX+', 'RX-'], [])
77 def ulpi(suffix
, bank
):
78 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
80 ulpipins
.append('D%d*' % i
)
84 def uartfull(suffix
, bank
):
85 return (['TX+', 'RX-', 'CTS-', 'RTS+'],
89 def rgbttl(suffix
, bank
):
90 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
92 ttlpins
.append("D%d+" % i
)
96 def rgmii(suffix
, bank
):
99 buspins
.append("ERXD%d-" % i
)
101 buspins
.append("ETXD%d+" % i
)
102 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
104 'ETXEN+', 'ETXCK+', 'ECRS-',
109 def flexbus1(suffix
, bank
):
114 buspins
.append(pname
)
117 buspins
.append("CS%d+" % i
)
118 buspins
+= ['ALE', 'OE', 'RW', 'TA', 'CLK+',
119 'A0', 'A1', 'TS', 'TBST',
122 buspins
.append("BWE%d" % i
)
123 for i
in range(2, 6):
124 buspins
.append("CS%d+" % i
)
125 return (buspins
, inout
)
128 def flexbus2(suffix
, bank
):
130 for i
in range(8, 32):
131 buspins
.append("AD%d*" % i
)
132 return (buspins
, buspins
)
135 def sdram1(suffix
, bank
):
139 pname
= "SDRDQM%d*" % i
140 buspins
.append(pname
)
143 buspins
.append("SDRAD%d+" % i
)
145 buspins
.append("SDRDQ%d+" % i
)
147 buspins
.append("SDRCS%d#+" % i
)
149 buspins
.append("SDRDQ%d+" % i
)
151 buspins
.append("SDRBA%d+" % i
)
152 buspins
+= ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
154 return (buspins
, inout
)
157 def sdram2(suffix
, bank
):
160 for i
in range(3, 6):
161 buspins
.append("SDRCS%d#+" % i
)
162 for i
in range(16, 32):
163 pname
= "SDRDQM%d*" % i
164 buspins
.append(pname
)
166 return (buspins
, inout
)
169 def mcu8080(suffix
, bank
):
173 pname
= "MCUD%d*" % i
174 buspins
.append(pname
)
177 buspins
.append("MCUAD%d+" % (i
+ 8))
179 buspins
.append("MCUCS%d+" % i
)
181 buspins
.append("MCUNRB%d+" % i
)
182 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
184 return (buspins
, inout
)
187 class RangePin(object):
188 def __init__(self
, suffix
, prefix
=None):
190 self
.prefix
= prefix
or ''
192 def __getitem__(self
, s
):
194 for idx
in range(s
.start
or 0, s
.stop
or -1, s
.step
or 1):
195 res
.append("%s%d%s" % (self
.prefix
, idx
, self
.suffix
))
199 def eint(suffix
, bank
):
200 return (RangePin("*"), [])
203 def pwm(suffix
, bank
):
204 return (RangePin("+"), [])
207 def gpio(suffix
, bank
):
208 return (("GPIO%s" % bank
, RangePin(prefix
=bank
, suffix
="*")), [])
211 # list functions by name here
213 pinspec
= (('IIS', i2s
),