src/spec/simple_gpio.py

   1 """Simple GPIO peripheral on wishbone
   2
   3 This is an extremely simple GPIO peripheral intended for use in XICS
   4 testing, however it could also be used as an actual GPIO peripheral
   5
   6 Modified for use with pinmux, will probably change the class name later.
   7 """
   8 from random import randint
   9 from nmigen import Elaboratable, Module, Signal, Record, Array
  10 from nmigen.hdl.rec import Layout
  11 from nmigen.utils import log2_int
  12 from nmigen.cli import rtlil
  13 from soc.minerva.wishbone import make_wb_layout
  14 from nmutil.util import wrap
  15 from soc.bus.test.wb_rw import wb_read, wb_write
  16
  17 cxxsim = False
  18 if cxxsim:
  19     from nmigen.sim.cxxsim import Simulator, Settle
  20 else:
  21     from nmigen.sim import Simulator, Settle
  22
  23 # Layout of 8-bit configuration word:
  24 # bank_select[2:0] i/o | pden puen ien oe
  25 OESHIFT = 0
  26 IESHIFT = 1
  27 PUSHIFT = 2
  28 PDSHIFT = 3
  29 IOSHIFT = 4
  30 BANKSHIFT = 5
  31 NUMBANKBITS = 3 # only supporting 8 banks (0-7)
  32
  33 # For future testing:
  34 WORDSIZE = 8 # in bytes
  35
  36 class SimpleGPIO(Elaboratable):
  37
  38     def __init__(self, n_gpio=16):
  39         self.n_gpio = n_gpio
  40         class Spec: pass
  41         spec = Spec()
  42         spec.addr_wid = 30
  43         spec.mask_wid = 4
  44         spec.reg_wid = 32
  45         self.bus = Record(make_wb_layout(spec), name="gpio_wb")
  46
  47         self.bank_sel = Array([Signal(NUMBANKBITS) for _ in range(n_gpio)])
  48         self.gpio_o = Signal(n_gpio)
  49         self.gpio_oe = Signal(n_gpio)
  50         self.gpio_i = Signal(n_gpio)
  51         self.gpio_ie = Signal(n_gpio)
  52         self.pden = Signal(n_gpio)
  53         self.puen = Signal(n_gpio)
  54
  55         layout = (("oe", 1),
  56                   ("ie", 1),
  57                   ("puen", 1),
  58                   ("pden", 1),
  59                   ("io", 1),
  60                   ("bank_sel", NUMBANKBITS)
  61                  )
  62         self.csrbus = Record(layout)
  63
  64     def elaborate(self, platform):
  65         m = Module()
  66         comb, sync = m.d.comb, m.d.sync
  67
  68         bus = self.bus
  69         wb_rd_data = bus.dat_r
  70         wb_wr_data = bus.dat_w
  71         wb_ack = bus.ack
  72
  73         bank_sel = self.bank_sel
  74         gpio_o = self.gpio_o
  75         gpio_oe = self.gpio_oe
  76         gpio_i = self.gpio_i
  77         gpio_ie = self.gpio_ie
  78         pden = self.pden
  79         puen = self.puen
  80         csrbus = self.csrbus
  81
  82         comb += wb_ack.eq(0)
  83
  84         gpio_addr = Signal(log2_int(self.n_gpio))
  85         gpio_o_list = Array(list(gpio_o))
  86         print(bank_sel)
  87         print(gpio_o_list)
  88         gpio_oe_list = Array(list(gpio_oe))
  89         gpio_i_list = Array(list(gpio_i))
  90         gpio_ie_list = Array(list(gpio_ie))
  91         pden_list = Array(list(pden))
  92         puen_list = Array(list(puen))
  93
  94         #print("Types:")
  95         #print("gpio_addr: ", type(gpio_addr))
  96         #print("gpio_o_list: ", type(gpio_o_list))
  97         #print("bank_sel: ", type(bank_sel))
  98
  99         # One address used to configure CSR, set output, read input
 100         with m.If(bus.cyc & bus.stb):
 101             comb += wb_ack.eq(1) # always ack
 102             comb += gpio_addr.eq(bus.adr)
 103             with m.If(bus.we): # write
 104                 # Configure CSR
 105                 sync += csrbus.eq(wb_wr_data)
 106             with m.Else(): # read
 107                 # Read the state of CSR bits
 108                 # Return state of input if ie
 109                 with m.If(gpio_ie_list[gpio_addr] == 1):
 110                     sync += csrbus.io.eq(gpio_i_list[gpio_addr])
 111                     comb += wb_rd_data.eq(csrbus)
 112                 # Return state of out if oe
 113                 with m.Else():
 114                     sync += csrbus.io.eq(gpio_o_list[gpio_addr])
 115                     comb += wb_rd_data.eq(csrbus)
 116
 117         # Combinatorial
 118         comb += gpio_oe_list[gpio_addr].eq(csrbus.oe)
 119         comb += gpio_ie_list[gpio_addr].eq(csrbus.ie)
 120         # Check to prevent output being set if GPIO configured as input
 121         # TODO: Is this necessary? PAD might deal with this
 122         # check GPIO is in output mode and NOT input (oe high, ie low)
 123         #with m.If(csrbus.oe & (~csrbus.ie)):
 124         with m.If(gpio_oe_list[gpio_addr] & (~gpio_ie_list[gpio_addr])):
 125             comb += gpio_o_list[gpio_addr].eq(csrbus.io)
 126         comb += puen_list[gpio_addr].eq(csrbus.puen)
 127         comb += pden_list[gpio_addr].eq(csrbus.pden)
 128         comb += bank_sel[gpio_addr].eq(csrbus.bank_sel)
 129         return m
 130
 131     def __iter__(self):
 132         for field in self.bus.fields.values():
 133             yield field
 134         yield self.gpio_o
 135
 136     def ports(self):
 137         return list(self)
 138
 139 # TODO: probably make into class (or return state in a variable)
 140 def gpio_configure(dut, gpio, oe, ie, puen, pden, outval, bank_sel):
 141     csr_val = ( (oe   << OESHIFT)
 142               | (ie   << IESHIFT)
 143               | (puen << PUSHIFT)
 144               | (pden << PDSHIFT)
 145               | (bank_sel << BANKSHIFT) )
 146     print("Configuring CSR to {0:x}".format(csr_val))
 147     yield from wb_write(dut.bus, gpio, csr_val)
 148     return csr_val # return the config state
 149
 150 def reg_write(dut, gpio, reg_val):
 151     print("Configuring CSR to {0:x}".format(reg_val))
 152     yield from wb_write(dut.bus, gpio, reg_val)
 153
 154 # TODO: Return the configuration states
 155 def gpio_rd_csr(dut, gpio):
 156     csr_val = yield from wb_read(dut.bus, gpio)
 157     print("GPIO{0} | CSR: {1:x}".format(gpio, csr_val))
 158     print("Output Enable: {0:b}".format((csr_val >> OESHIFT) & 1))
 159     print("Input Enable: {0:b}".format((csr_val >> IESHIFT) & 1))
 160     print("Pull-Up Enable: {0:b}".format((csr_val >> PUSHIFT) & 1))
 161     print("Pull-Down Enable: {0:b}".format((csr_val >> PDSHIFT) & 1))
 162     if ((csr_val >> IESHIFT) & 1):
 163         print("Input: {0:b}".format((csr_val >> IOSHIFT) & 1))
 164     else:
 165         print("Output: {0:b}".format((csr_val >> IOSHIFT) & 1))
 166     print("Bank Select: {0:b}".format((csr_val >> BANKSHIFT) & 1))
 167     # gpio_parse_csr(csr_val)
 168     return csr_val
 169
 170 # TODO
 171 def gpio_rd_input(dut, gpio):
 172     in_val = yield from wb_read(dut.bus, gpio)
 173     in_val = (in_val >> IOSHIFT) & 1
 174     print("GPIO{0} | Input: {1:b}".format(gpio, in_val))
 175     return in_val
 176
 177 def gpio_set_out(dut, gpio, csr_val, output):
 178     print("Setting GPIO{0} output to {1}".format(gpio, output))
 179     yield from wb_write(dut.bus, gpio, csr_val | (output<<IOSHIFT))
 180
 181 # TODO: There's probably a cleaner way to clear the bit...
 182 def gpio_set_in_pad(dut, gpio, in_val):
 183     old_in_val = yield dut.gpio_i
 184     if in_val:
 185         new_in_val = old_in_val | (in_val << gpio)
 186     else:
 187         temp = (old_in_val >> gpio) & 1
 188         if temp:
 189             mask = ~(1 << gpio)
 190             new_in_val = old_in_val & mask
 191         else:
 192             new_in_val = old_in_val
 193     print("Previous GPIO i: {0:b} | New GPIO i: {1:b}"
 194           .format(old_in_val, new_in_val))
 195     yield dut.gpio_i.eq(new_in_val)
 196
 197 def gpio_test_in_pattern(dut, pattern):
 198     num_gpios = len(dut.gpio_o)
 199     print("Test pattern:")
 200     print(pattern)
 201     for pat in range(0, len(pattern)):
 202         for gpio in range(0, num_gpios):
 203             yield from gpio_set_in_pad(dut, gpio, pattern[pat])
 204             yield
 205             temp = yield from gpio_rd_input(dut, gpio)
 206             print("Pattern: {0}, Reading {1}".format(pattern[pat], temp))
 207             assert (temp == pattern[pat])
 208             pat += 1
 209             if pat == len(pattern):
 210                 break
 211
 212
 213 def sim_gpio(dut, use_random=True):
 214     print(dir(dut))
 215     print(dut)
 216     num_gpios = len(dut.gpio_o)
 217     if use_random:
 218         bank_sel = randint(0, 2**NUMBANKBITS)
 219         print("Random bank_select: {0:b}".format(bank_sel))
 220     else:
 221         bank_sel = 3 # not special, chose for testing
 222     oe = 1
 223     ie = 0
 224     output = 0
 225     puen = 0 # 1
 226     pden = 0
 227     gpio_csr = [0] * num_gpios
 228     # Configure GPIOs for
 229     for gpio in range(0, 1): #num_gpios):
 230         gpio_csr[gpio] = yield from gpio_configure(dut, gpio, oe, ie, puen,
 231                                                    pden, output, bank_sel)
 232     # Set outputs
 233     for gpio in range(0, 1): #num_gpios):
 234         yield from gpio_set_out(dut, gpio, gpio_csr[gpio], 1)
 235
 236     # Read CSR
 237     for gpio in range(0, 1): #num_gpios):
 238         yield from gpio_rd_csr(dut, gpio)
 239
 240     # Configure for input
 241     oe = 0
 242     ie = 1
 243     gpio_csr[0] = yield from gpio_configure(dut, 0, oe, ie, puen,
 244                                             pden, output, bank_sel)
 245     # Input testing
 246     yield from gpio_set_in_pad(dut, 0, 1)
 247     yield
 248     temp = yield from gpio_rd_input(dut, 0)
 249     yield
 250
 251     # TODO: not working yet
 252     #test_pattern = []
 253     #for i in range(0, (num_gpios * 2)):
 254     #    test_pattern.append(randint(0,1))
 255     #yield from gpio_test_in_pattern(dut, test_pattern)
 256
 257     #reg_val = 0x32
 258     #yield from reg_write(dut, 0, reg_val)
 259     #yield from reg_write(dut, 0, reg_val)
 260     #yield
 261     print("Finished the simple GPIO block test!")
 262
 263 def test_gpio():
 264     dut = SimpleGPIO()
 265     vl = rtlil.convert(dut, ports=dut.ports())
 266     with open("test_gpio.il", "w") as f:
 267         f.write(vl)
 268
 269     m = Module()
 270     m.submodules.xics_icp = dut
 271
 272     sim = Simulator(m)
 273     sim.add_clock(1e-6)
 274
 275     sim.add_sync_process(wrap(sim_gpio(dut, use_random=False)))
 276     sim_writer = sim.write_vcd('test_gpio.vcd')
 277     with sim_writer:
 278         sim.run()
 279
 280
 281 if __name__ == '__main__':
 282     test_gpio()
 283