src/spec/simple_gpio.py

   1 """Simple GPIO peripheral on wishbone
   2
   3 This is an extremely simple GPIO peripheral intended for use in XICS
   4 testing, however it could also be used as an actual GPIO peripheral
   5
   6 Modified for use with pinmux, will probably change the class name later.
   7 """
   8 from random import randint
   9 from math import ceil, floor
  10 from nmigen import Elaboratable, Module, Signal, Record, Array, Cat, Const
  11 from nmigen.hdl.rec import Layout
  12 from nmigen.utils import log2_int
  13 from nmigen.cli import rtlil
  14 from soc.minerva.wishbone import make_wb_layout
  15 from nmutil.util import wrap
  16 from soc.bus.test.wb_rw import wb_read, wb_write
  17
  18 from nmutil.gtkw import write_gtkw
  19
  20 cxxsim = False
  21 if cxxsim:
  22     from nmigen.sim.cxxsim import Simulator, Settle
  23 else:
  24     from nmigen.sim import Simulator, Settle
  25
  26 # Layout of 8-bit configuration word:
  27 # bank[2:0] i/o | pden puen ien oe
  28 NUMBANKBITS = 3 # max 3 bits, only supporting 4 banks (0-3)
  29 csrbus_layout = (("oe", 1),
  30                  ("ie", 1),
  31                  ("puen", 1),
  32                  ("pden", 1),
  33                  ("io", 1),
  34                  ("bank", NUMBANKBITS)
  35                 )
  36
  37 gpio_layout = (("i", 1),
  38                ("oe", 1),
  39                ("o", 1),
  40                ("puen", 1),
  41                ("pden", 1),
  42                ("bank", NUMBANKBITS)
  43               )
  44
  45 class SimpleGPIO(Elaboratable):
  46
  47     def __init__(self, wordsize=4, n_gpio=16):
  48         self.wordsize = wordsize
  49         self.n_gpio = n_gpio
  50         self.n_rows = ceil(self.n_gpio / self.wordsize)
  51         print("SimpleGPIO: WB Data # of bytes: {0}, #GPIOs: {1}, Rows: {2}"
  52               .format(self.wordsize, self.n_gpio, self.n_rows))
  53         class Spec: pass
  54         spec = Spec()
  55         spec.addr_wid = 30
  56         spec.mask_wid = 4
  57         spec.reg_wid = wordsize*8 # 32
  58         self.bus = Record(make_wb_layout(spec), name="gpio_wb")
  59         #self.wb_rd_data_reg = Signal(self.wordsize*8) # same len as WB bus
  60
  61         #print("CSRBUS layout: ", csrbus_layout)
  62         # MultiCSR read and write buses
  63         temp = []
  64         for i in range(self.wordsize):
  65             temp_str = "rd_word{}".format(i)
  66             temp.append(Record(name=temp_str, layout=csrbus_layout))
  67         self.rd_multicsr = Array(temp)
  68
  69         temp = []
  70         for i in range(self.wordsize):
  71             temp_str = "word{}".format(i)
  72             temp.append(Record(name=temp_str, layout=csrbus_layout))
  73         self.multicsrbus = Array(temp)
  74
  75         temp = []
  76         for i in range(self.n_gpio):
  77             temp_str = "gpio{}".format(i)
  78             temp.append(Record(name=temp_str, layout=gpio_layout))
  79         self.gpio_ports = Array(temp)
  80
  81     def elaborate(self, platform):
  82         m = Module()
  83         comb, sync = m.d.comb, m.d.sync
  84
  85         bus = self.bus
  86         wb_rd_data = bus.dat_r
  87         wb_wr_data = bus.dat_w
  88         #wb_rd_data_reg = self.wb_rd_data_reg
  89         wb_ack = bus.ack
  90
  91         gpio_ports = self.gpio_ports
  92         multi = self.multicsrbus
  93         rd_multi = self.rd_multicsr
  94
  95         # Flag for indicating rd/wr transactions
  96         new_transaction = Signal(1)
  97
  98         # One address used to configure CSR, set output, read input
  99         with m.If(bus.cyc & bus.stb):
 100             # TODO: is this needed anymore?
 101             sync += new_transaction.eq(1)
 102             # Concatinate the GPIO configs that are on the same "row" or
 103             # address and send
 104             #multi_cat = []
 105             #for i in range(0, self.wordsize):
 106             #    multi_cat.append(rd_multi[i])
 107             #sync += wb_rd_data_reg.eq(Cat(multi_cat))
 108             with m.If(bus.we): # write
 109                 sync += wb_ack.eq(1) # always ack, always delayed
 110                 # Configure CSR
 111                 for byte in range(0, self.wordsize):
 112                     # TODO: wasteful... convert to Cat(), somehow
 113                     sync += multi[byte].eq(wb_wr_data[byte*8:8+byte*8])
 114                 # sync += Cat(*multi).eq(wb_wr_data)
 115             with m.Else():
 116                 self.connect_gpio_to_rd_bus(m, sync, bus.adr, gpio_ports,
 117                                             rd_multi)
 118         with m.Else():
 119             sync += new_transaction.eq(0)
 120             sync += wb_ack.eq(0)
 121
 122         # Only update GPIOs config if a new transaction happened last cy=cle
 123         # (read or write). Always lags from multi csrbus by 1 clk cycle, most
 124         # sane way I could think of while using Record().
 125         with m.If(new_transaction):
 126             with m.If(bus.we):
 127                 self.connect_wr_bus_to_gpio(m, sync, bus.adr, gpio_ports, multi)
 128                 sync += wb_ack.eq(0)
 129             with m.Else():
 130                 multi_cat = []
 131                 for i in range(0, self.wordsize):
 132                     multi_cat.append(rd_multi[i])
 133                 sync += wb_rd_data.eq(Cat(multi_cat))
 134                 sync += wb_ack.eq(1) # Delay ack until rd data is ready!
 135
 136
 137         return m
 138
 139     def connect_wr_bus_to_gpio(self, module, domain, addr, gp, multi):
 140         if self.n_gpio > self.wordsize:
 141             print("#GPIOs is greater than, and is a multiple of WB wordsize")
 142             # Case where all gpios fit within full words
 143             if self.n_gpio % self.wordsize == 0:
 144                 for byte in range(self.wordsize):
 145                     with module.If(addr[0]):
 146                         self.wr_connect_one_byte(module, domain, gp, multi,
 147                                                  byte, self.wordsize)
 148                     with module.Else():
 149                         self.wr_connect_one_byte(module, domain, gp, multi,
 150                                                  byte, 0)
 151             else:
 152                 # TODO: This is a complex case, not needed atm
 153                 print("#GPIOs is greater than WB wordsize")
 154                 print("But not fully fitting in words...")
 155                 print("NOT IMPLEMENTED THIS CASE")
 156                 raise
 157         else:
 158             print("#GPIOs is less or equal to WB wordsize (in bytes)")
 159             for byte in range(self.n_gpio):
 160                 self.wr_connect_one_byte(module, domain, gp, multi, byte, 0)
 161
 162     def connect_gpio_to_rd_bus(self, module, domain, addr, gp, multi):
 163         if self.n_gpio > self.wordsize:
 164             print("#GPIOs is greater than, and is a multiple of WB wordsize")
 165             # Case where all gpios fit within full words
 166             if self.n_gpio % self.wordsize == 0:
 167                 for byte in range(self.wordsize):
 168                     with module.If(addr[0]):
 169                         self.rd_connect_one_byte(module, domain, gp, multi, byte, self.wordsize)
 170                     with module.Else():
 171                         self.rd_connect_one_byte(module, domain, gp, multi, byte, 0)
 172             else:
 173                 # TODO: This is a complex case, not needed atm
 174                 print("#GPIOs is greater than WB wordsize")
 175                 print("NOT IMPLEMENTED THIS CASE")
 176                 raise
 177         else:
 178             print("#GPIOs is less or equal to WB wordsize (in bytes)")
 179             for byte in range(self.n_gpio):
 180                 self.rd_connect_one_byte(module, domain, gp, multi, byte, 0)
 181
 182     def rd_connect_one_byte(self, module, domain, gp, multi, byte, offset):
 183         domain += multi[byte].oe.eq(gp[byte+offset].oe)
 184         domain += multi[byte].puen.eq(gp[byte+offset].puen)
 185         domain += multi[byte].pden.eq(gp[byte+offset].pden)
 186         with module.If(gp[byte+offset].oe):
 187             domain += multi[byte].ie.eq(0)
 188             domain += multi[byte].io.eq(gp[byte+offset].o)
 189         with module.Else():
 190             domain += multi[byte].ie.eq(1) # Return GPIO as i by default
 191             domain += multi[byte].io.eq(gp[byte+offset].i)
 192
 193         domain += multi[byte].bank.eq(gp[byte+offset].bank)
 194
 195     def wr_connect_one_byte(self, module, domain, gp, multi, byte, offset):
 196         domain += gp[byte+offset].oe.eq(multi[byte].oe)
 197         domain += gp[byte+offset].puen.eq(multi[byte].puen)
 198         domain += gp[byte+offset].pden.eq(multi[byte].pden)
 199         # prevent output being set if GPIO configured as i
 200         # TODO: No checking is done if ie/oe high together
 201         with module.If(multi[byte].oe):
 202             domain += gp[byte+offset].o.eq(multi[byte].io)
 203         with module.Else():
 204             domain += gp[byte+offset].o.eq(0)
 205         domain += gp[byte+offset].bank.eq(multi[byte].bank)
 206
 207
 208     def __iter__(self):
 209         for field in self.bus.fields.values():
 210             yield field
 211         for gpio in range(len(self.gpio_ports)):
 212             for field in self.gpio_ports[gpio].fields.values():
 213                 yield field
 214
 215     def ports(self):
 216         return list(self)
 217
 218 """
 219 def gpio_test_in_pattern(dut, pattern):
 220     num_gpios = len(dut.gpio_ports)
 221     print("Test pattern:")
 222     print(pattern)
 223     for pat in range(0, len(pattern)):
 224         for gpio in range(0, num_gpios):
 225             yield gpio_set_in_pad(dut, gpio, pattern[pat])
 226             yield
 227             temp = yield from gpio_rd_input(dut, gpio)
 228             print("Pattern: {0}, Reading {1}".format(pattern[pat], temp))
 229             assert (temp == pattern[pat])
 230             pat += 1
 231             if pat == len(pattern):
 232                 break
 233 """
 234
 235 def test_gpio_single(dut, gpio, use_random=True):
 236     oe = 1
 237     ie = 0
 238     output = 0
 239     puen = 0
 240     pden = 0
 241     if use_random:
 242         bank = randint(0, (2**NUMBANKBITS)-1)
 243         print("Random bank select: {0:b}".format(bank))
 244     else:
 245         bank = 3 # not special, chose for testing
 246
 247     gpio_csr = yield from gpio_config(dut, gpio, oe, ie, puen, pden, output,
 248                                       bank, check=True)
 249     # Enable output
 250     output = 1
 251     gpio_csr = yield from gpio_config(dut, gpio, oe, ie, puen, pden, output,
 252                                       bank, check=True)
 253
 254 # Shadow reg container class
 255 class GPIOConfigReg():
 256     def __init__(self, shift_dict):
 257         self.shift_dict = shift_dict
 258         self.oe=0
 259         self.ie=0
 260         self.puen=0
 261         self.pden=0
 262         self.io=0
 263         self.bank=0
 264         self.packed=0
 265
 266     def set(self, oe=0, ie=0, puen=0, pden=0, io=0, bank=0):
 267         self.oe=oe
 268         self.ie=ie
 269         self.puen=puen
 270         self.pden=pden
 271         self.io=io
 272         self.bank=bank
 273         self.pack() # Produce packed byte for sending
 274
 275     def set_out(self, outval):
 276         self.io=outval
 277         self.pack() # Produce packed byte for sending
 278
 279     # Take config parameters of specified GPIOs, and combine them to produce
 280     # bytes for sending via WB bus
 281     def pack(self):
 282         self.packed = ((self.oe   << self.shift_dict['oe'])
 283                      | (self.ie   << self.shift_dict['ie'])
 284                      | (self.puen << self.shift_dict['puen'])
 285                      | (self.pden << self.shift_dict['pden'])
 286                      | (self.io   << self.shift_dict['io'])
 287                      | (self.bank << self.shift_dict['bank']))
 288
 289         #print("GPIO Packed CSR: {0:x}".format(self.packed))
 290
 291 # Object for storing each gpio's config state
 292
 293 class GPIOManager():
 294     def __init__(self, dut, layout, wb_bus):
 295         self.dut = dut
 296         self.wb_bus = wb_bus
 297         # arrangement of config bits making up csr word
 298         self.csr_layout = layout
 299         self.shift_dict = self._create_shift_dict()
 300         self.n_gpios = len(self.dut.gpio_ports)
 301         print(dir(self.dut))
 302         # Since GPIO HDL block already has wordsize parameter, use directly
 303         # Alternatively, can derive from WB data r/w buses (div by 8 for bytes)
 304         #self.wordsize = len(self.dut.gpio_wb__dat_w) / 8
 305         self.wordsize = self.dut.wordsize
 306         self.n_rows = ceil(self.n_gpios / self.wordsize)
 307         self.shadow_csr = []
 308         for i in range(self.n_gpios):
 309             self.shadow_csr.append(GPIOConfigReg(self.shift_dict))
 310
 311     def print_info(self):
 312         print("----------")
 313         print("GPIO Block Info:")
 314         print("Number of GPIOs: {}".format(self.n_gpios))
 315         print("WB Data bus width (in bytes): {}".format(self.wordsize))
 316         print("Number of rows: {}".format(self.n_rows))
 317         print("----------")
 318
 319     # The shifting of control bits in the configuration word is dependent on the
 320     # defined layout. To prevent maintaining the shift constants in a separate
 321     # location, the same layout is used to generate a dictionary of bit shifts
 322     # with which the configuration word can be produced!
 323     def _create_shift_dict(self):
 324         shift = 0
 325         shift_dict = {}
 326         for i in range(0, len(self.csr_layout)):
 327             shift_dict[self.csr_layout[i][0]] = shift
 328             shift += self.csr_layout[i][1]
 329         print(shift_dict)
 330         return shift_dict
 331
 332     def _parse_gpio_arg(self, gpio_str):
 333         # TODO: No input checking!
 334         print("Given GPIO/range string: {}".format(gpio_str))
 335         if gpio_str == "all":
 336             start = 0
 337             end = self.n_gpios
 338         elif '-' in gpio_str:
 339             start, end = gpio_str.split('-')
 340             start = int(start)
 341             end = int(end) + 1
 342             if (end < start) or (end > self.n_gpios):
 343                 raise Exception("Second GPIO must be higher than first and"
 344                         + " must be lower or equal to last available GPIO.")
 345         else:
 346             start = int(gpio_str)
 347             if start >= self.n_gpios:
 348                 raise Exception("GPIO must be less/equal to last GPIO.")
 349             end = start + 1
 350         print("Parsed GPIOs {0} until {1}".format(start, end))
 351         return start, end
 352
 353     # Take a combined word and update shadow reg's
 354     # TODO: convert hard-coded sizes to use the csrbus_layout (or dict?)
 355     def update_single_shadow(self, csr_byte, gpio):
 356         oe   = (csr_byte >> self.shift_dict['oe']) & 0x1
 357         ie   = (csr_byte >> self.shift_dict['ie']) & 0x1
 358         puen = (csr_byte >> self.shift_dict['puen']) & 0x1
 359         pden = (csr_byte >> self.shift_dict['pden']) & 0x1
 360         io   = (csr_byte >> self.shift_dict['io']) & 0x1
 361         bank = (csr_byte >> self.shift_dict['bank']) & 0x3
 362
 363         print("csr={0:x} | oe={1}, ie={2}, puen={3}, pden={4}, io={5}, bank={6}"
 364               .format(csr_byte, oe, ie, puen, pden, io, bank))
 365
 366         self.shadow_csr[gpio].set(oe, ie, puen, pden, io, bank)
 367         return oe, ie, puen, pden, io, bank
 368
 369     def rd_csr(self, row_start):
 370         row_word = yield from wb_read(self.wb_bus, row_start)
 371         print("Returned CSR: {0:x}".format(row_word))
 372         return row_word
 373
 374     # Update a single row of configuration registers
 375     def wr_row(self, row_addr, check=False):
 376         curr_gpio = row_addr * self.wordsize
 377         config_word = 0
 378         for byte in range(0, self.wordsize):
 379             if curr_gpio >= self.n_gpios:
 380                 break
 381             config_word += self.shadow_csr[curr_gpio].packed << (8 * byte)
 382             #print("Reading GPIO{} shadow reg".format(curr_gpio))
 383             curr_gpio += 1
 384         print("Writing shadow CSRs val {0:x}  to row addr {1:x}"
 385               .format(config_word, row_addr))
 386         yield from wb_write(self.wb_bus, row_addr, config_word)
 387         yield # Allow one clk cycle to propagate
 388
 389         if(check):
 390             read_word = yield from self.rd_row(row_addr)
 391             assert config_word == read_word
 392
 393     # Read a single address row of GPIO CSRs, and update shadow
 394     def rd_row(self, row_addr):
 395         read_word = yield from self.rd_csr(row_addr)
 396         curr_gpio = row_addr * self.wordsize
 397         single_csr = 0
 398         for byte in range(0, self.wordsize):
 399             if curr_gpio >= self.n_gpios:
 400                 break
 401             single_csr = (read_word >> (8 * byte)) & 0xFF
 402             #print("Updating GPIO{0} shadow reg to {1:x}"
 403             #      .format(curr_gpio, single_csr))
 404             self.update_single_shadow(single_csr, curr_gpio)
 405             curr_gpio += 1
 406         return read_word
 407
 408     # Write all shadow registers to GPIO block
 409     def wr_all(self, check=False):
 410         for row in range(0, self.n_rows):
 411             yield from self.wr_row(row, check)
 412
 413     # Read all GPIO block row addresses and update shadow reg's
 414     def rd_all(self, check=False):
 415         for row in range(0, self.n_rows):
 416             yield from self.rd_row(row, check)
 417
 418     def config(self, gpio_str, oe, ie, puen, pden, outval, bank, check=False):
 419         start, end = self._parse_gpio_arg(gpio_str)
 420         # Update the shadow configuration
 421         for gpio in range(start, end):
 422             # print(oe, ie, puen, pden, outval, bank)
 423             self.shadow_csr[gpio].set(oe, ie, puen, pden, outval, bank)
 424         # TODO: only update the required rows?
 425         yield from self.wr_all()
 426
 427     # Set/Clear the output bit for single or group of GPIOs
 428     def set_out(self, gpio_str, outval):
 429         start, end = self._parse_gpio_arg(gpio_str)
 430         for gpio in range(start, end):
 431             self.shadow_csr[gpio].set_out(outval)
 432
 433         if start == end:
 434             print("Setting GPIO{0} output to {1}".format(start, outval))
 435         else:
 436             print("Setting GPIOs {0}-{1} output to {2}"
 437                   .format(start, end-1, outval))
 438
 439         yield from self.wr_all()
 440
 441     def rd_input(self, gpio_str): # REWORK
 442         start, end = self._parse_gpio_arg(gpio_str)
 443         curr_gpio = 0
 444         # Too difficult to think about, just read all configs
 445         #start_row = floor(start / self.wordsize)
 446         # Hack because end corresponds to range limit, but maybe on same row
 447         # TODO: clean
 448         #end_row = floor( (end-1) / self.wordsize) + 1
 449         read_data = [0] * self.n_rows
 450         for row in range(0, self.n_rows):
 451             read_data[row] = yield from self.rd_row(row)
 452
 453         num_to_read = (end - start)
 454         read_in = [0] * num_to_read
 455         curr_gpio = 0
 456         for i in range(0, num_to_read):
 457             read_in[i] = self.shadow_csr[curr_gpio].io
 458             curr_gpio += 1
 459
 460         print("GPIOs {0} until {1}, i={2}".format(start, end, read_in))
 461         return read_in
 462
 463     # TODO: There's probably a cleaner way to clear the bit...
 464     def sim_set_in_pad(self, gpio_str, in_val):
 465         start, end = self._parse_gpio_arg(gpio_str)
 466         for gpio in range(start, end):
 467             old_in_val = yield self.dut.gpio_ports[gpio].i
 468             print(old_in_val)
 469             print("GPIO{0} Previous i: {1:b} | New i: {2:b}"
 470                   .format(gpio, old_in_val, in_val))
 471             yield self.dut.gpio_ports[gpio].i.eq(in_val)
 472             yield # Allow one clk cycle to propagate
 473
 474     def rd_shadow(self):
 475         shadow_csr = [0] * self.n_gpios
 476         for gpio in range(0, self.n_gpios):
 477             shadow_csr[gpio] = self.shadow_csr[gpio].packed
 478
 479         hex_str = ""
 480         for reg in shadow_csr:
 481             hex_str += " "+hex(reg)
 482         print("Shadow reg's: ", hex_str)
 483
 484         return shadow_csr
 485
 486
 487 def sim_gpio(dut, use_random=True):
 488     #print(dut)
 489     #print(dir(dut.gpio_ports))
 490     #print(len(dut.gpio_ports))
 491
 492     gpios = GPIOManager(dut, csrbus_layout)
 493     gpios.print_info()
 494     # TODO: not working yet
 495     #test_pattern = []
 496     #for i in range(0, (num_gpios * 2)):
 497     #    test_pattern.append(randint(0,1))
 498     #yield from gpio_test_in_pattern(dut, test_pattern)
 499
 500     #yield from gpio_config(dut, start_gpio, oe, ie, puen, pden, outval, bank, end_gpio, check=False, wordsize=4)
 501     #reg_val = 0xC56271A2
 502     #reg_val =  0xFFFFFFFF
 503     #yield from reg_write(dut, 0, reg_val)
 504     #yield from reg_write(dut, 0, reg_val)
 505     #yield
 506
 507     #csr_val = yield from wb_read(dut.bus, 0)
 508     #print("CSR Val: {0:x}".format(csr_val))
 509     print("Finished the simple GPIO block test!")
 510
 511 def gen_gtkw_doc(n_gpios, wordsize, filename):
 512     # GTKWave doc generation
 513     wb_data_width = wordsize*8
 514     n_rows = ceil(n_gpios/wordsize)
 515     style = {
 516         '': {'base': 'hex'},
 517         'in': {'color': 'orange'},
 518         'out': {'color': 'yellow'},
 519         'debug': {'module': 'top', 'color': 'red'}
 520     }
 521
 522     # Create a trace list, each block expected to be a tuple()
 523     traces = []
 524     wb_traces = ('Wishbone Bus', [
 525                         ('gpio_wb__cyc', 'in'),
 526                         ('gpio_wb__stb', 'in'),
 527                         ('gpio_wb__we', 'in'),
 528                         ('gpio_wb__adr[27:0]', 'in'),
 529                         ('gpio_wb__dat_w[{}:0]'.format(wb_data_width-1), 'in'),
 530                         ('gpio_wb__dat_r[{}:0]'.format(wb_data_width-1), 'out'),
 531                         ('gpio_wb__ack', 'out'),
 532                 ])
 533     traces.append(wb_traces)
 534
 535     gpio_internal_traces = ('Internal', [
 536                                 ('clk', 'in'),
 537                                 ('new_transaction'),
 538                                 ('rst', 'in')
 539                             ])
 540     traces.append(gpio_internal_traces)
 541
 542     traces.append({'comment': 'Multi-byte GPIO config read bus'})
 543     for word in range(0, wordsize):
 544         prefix = "rd_word{}__".format(word)
 545         single_word = []
 546         word_signals = []
 547         single_word.append('Word{}'.format(word))
 548         word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1)))
 549         word_signals.append((prefix+'ie'))
 550         word_signals.append((prefix+'io'))
 551         word_signals.append((prefix+'oe'))
 552         word_signals.append((prefix+'pden'))
 553         word_signals.append((prefix+'puen'))
 554         single_word.append(word_signals)
 555         traces.append(tuple(single_word))
 556
 557     traces.append({'comment': 'Multi-byte GPIO config bus'})
 558     for word in range(0, wordsize):
 559         prefix = "word{}__".format(word)
 560         single_word = []
 561         word_signals = []
 562         single_word.append('Word{}'.format(word))
 563         word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1)))
 564         word_signals.append((prefix+'ie'))
 565         word_signals.append((prefix+'io'))
 566         word_signals.append((prefix+'oe'))
 567         word_signals.append((prefix+'pden'))
 568         word_signals.append((prefix+'puen'))
 569         single_word.append(word_signals)
 570         traces.append(tuple(single_word))
 571
 572     for gpio in range(0, n_gpios):
 573         prefix = "gpio{}__".format(gpio)
 574         single_gpio = []
 575         gpio_signals = []
 576         single_gpio.append('GPIO{} Port'.format(gpio))
 577         gpio_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1), 'out'))
 578         gpio_signals.append( (prefix+'i', 'in') )
 579         gpio_signals.append( (prefix+'o', 'out') )
 580         gpio_signals.append( (prefix+'oe', 'out') )
 581         gpio_signals.append( (prefix+'pden', 'out') )
 582         gpio_signals.append( (prefix+'puen', 'out') )
 583         single_gpio.append(gpio_signals)
 584         traces.append(tuple(single_gpio))
 585
 586     #print(traces)
 587
 588     write_gtkw(filename+".gtkw", filename+".vcd", traces, style,
 589                module="top.xics_icp")
 590
 591 def test_gpio():
 592     filename = "test_gpio" # Doesn't include extension
 593     n_gpios = 8
 594     wordsize = 4 # Number of bytes in the WB data word
 595     dut = SimpleGPIO(wordsize, n_gpios)
 596     vl = rtlil.convert(dut, ports=dut.ports())
 597     with open(filename+".il", "w") as f:
 598         f.write(vl)
 599
 600     m = Module()
 601     m.submodules.xics_icp = dut
 602
 603     sim = Simulator(m)
 604     sim.add_clock(1e-6)
 605
 606     #sim.add_sync_process(wrap(sim_gpio(dut, use_random=False)))
 607     sim.add_sync_process(wrap(test_gpioman(dut)))
 608     sim_writer = sim.write_vcd(filename+".vcd")
 609     with sim_writer:
 610         sim.run()
 611
 612     gen_gtkw_doc(n_gpios, wordsize, filename)
 613
 614 def test_gpioman(dut):
 615     print("------START----------------------")
 616     gpios = GPIOManager(dut, csrbus_layout, dut.bus)
 617     gpios.print_info()
 618     #gpios._parse_gpio_arg("all")
 619     #gpios._parse_gpio_arg("0")
 620     #gpios._parse_gpio_arg("1-3")
 621     #gpios._parse_gpio_arg("20")
 622
 623     oe = 1
 624     ie = 0
 625     puen = 0
 626     pden = 1
 627     outval = 0
 628     bank = 3
 629     yield from gpios.config("0-3", oe=1, ie=0, puen=0, pden=1, outval=0, bank=2)
 630     ie = 1
 631     yield from gpios.config("4-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=6)
 632     yield from gpios.set_out("0-1", outval=1)
 633
 634     #yield from gpios.rd_all()
 635     yield from gpios.sim_set_in_pad("6-7", 1)
 636     print("----------------------------")
 637     yield from gpios.rd_input("4-7")
 638
 639     gpios.rd_shadow()
 640
 641 if __name__ == '__main__':
 642     test_gpio()
 643