src/spec/testing_stage1.py

   1 #!/usr/bin/env python3
   2 """
   3 pinmux documented here https://libre-soc.org/docs/pinmux/
   4 """
   5 from nmigen.build.dsl import Resource, Subsignal, Pins
   6 from nmigen.build.plat import TemplatedPlatform
   7 from nmigen.build.res import ResourceManager, ResourceError
   8 from nmigen.hdl.rec import Layout
   9 from nmigen import Elaboratable, Signal, Module, Instance
  10 from collections import OrderedDict
  11 from jtag import JTAG, resiotypes
  12 from copy import deepcopy
  13 from nmigen.cli import rtlil
  14 import sys
  15
  16 # extra dependencies for jtag testing (?)
  17 #from soc.bus.sram import SRAM
  18
  19 #from nmigen import Memory
  20 from nmigen.sim import Simulator, Delay, Settle, Tick, Passive
  21
  22 from nmutil.util import wrap
  23
  24 #from soc.debug.jtagutils import (jtag_read_write_reg,
  25 #                                 jtag_srv, jtag_set_reset,
  26 #                                 jtag_set_ir, jtag_set_get_dr)
  27
  28 from c4m.nmigen.jtag.tap import TAP, IOType
  29 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
  30 #from soc.debug.dmi import DMIInterface, DBGCore
  31 #from soc.debug.test.dmi_sim import dmi_sim
  32 #from soc.debug.test.jtagremote import JTAGServer, JTAGClient
  33 from nmigen.build.res import ResourceError
  34
  35 # Was thinking of using these functions, but skipped for simplicity for now
  36 # XXX nope.  the output from JSON file.
  37 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
  38 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
  39 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
  40
  41 # File for stage 1 pinmux tested proposed by Luke,
  42 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
  43
  44
  45 def dummy_pinset():
  46     # sigh this needs to come from pinmux.
  47     gpios = []
  48     for i in range(4):
  49         gpios.append("%d*" % i)
  50     return {'uart': ['tx+', 'rx-'],
  51             'gpio': gpios,
  52             #'jtag': ['tms-', 'tdi-', 'tdo+', 'tck+'],
  53             'i2c': ['sda*', 'scl+']}
  54
  55 """
  56 a function is needed which turns the results of dummy_pinset()
  57 into:
  58
  59 [UARTResource("uart", 0, tx=..., rx=..),
  60  I2CResource("i2c", 0, scl=..., sda=...),
  61  Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
  62  Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
  63  ...
  64 ]
  65 """
  66
  67
  68 def create_resources(pinset):
  69     resources = []
  70     for periph, pins in pinset.items():
  71         print(periph, pins)
  72         if periph == 'i2c':
  73             #print("I2C required!")
  74             resources.append(I2CResource('i2c', 0, sda='sda', scl='scl'))
  75         elif periph == 'uart':
  76             #print("UART required!")
  77             resources.append(UARTResource('uart', 0, tx='tx', rx='rx'))
  78         elif periph == 'gpio':
  79             #print("GPIO required!")
  80             print ("GPIO is defined as '*' type, meaning i, o and oe needed")
  81             ios = []
  82             for pin in pins:
  83                 pname = "gpio"+pin[:-1] # strip "*" on end
  84                 # urrrr... tristsate and io assume a single pin which is
  85                 # of course exactly what we don't want in an ASIC: we want
  86                 # *all three* pins but the damn port is not outputted
  87                 # as a triplet, it's a single Record named "io". sigh.
  88                 # therefore the only way to get a triplet of i/o/oe
  89                 # is to *actually* create explicit triple pins
  90                 # XXX ARRRGH, doesn't work
  91                 #pad = Subsignal("io",
  92                 #            Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
  93                 #                 dir="io", assert_width=3))
  94                 #ios.append(Resource(pname, 0, pad))
  95                 pads = []
  96                 pads.append(Subsignal("i",
  97                             Pins(pname+"_i", dir="i", assert_width=1)))
  98                 pads.append(Subsignal("o",
  99                             Pins(pname+"_o", dir="o", assert_width=1)))
 100                 pads.append(Subsignal("oe",
 101                             Pins(pname+"_oe", dir="o", assert_width=1)))
 102                 ios.append(Resource.family(pname, 0, default_name=pname,
 103                                                  ios=pads))
 104             resources.append(Resource.family(periph, 0, default_name="gpio",
 105                                              ios=ios))
 106
 107     # add clock and reset
 108     clk = Resource("clk", 0, Pins("sys_clk", dir="i"))
 109     rst = Resource("rst", 0, Pins("sys_rst", dir="i"))
 110     resources.append(clk)
 111     resources.append(rst)
 112     return resources
 113
 114
 115 def JTAGResource(*args):
 116     io = []
 117     io.append(Subsignal("tms", Pins("tms", dir="i", assert_width=1)))
 118     io.append(Subsignal("tdi", Pins("tdi", dir="i", assert_width=1)))
 119     io.append(Subsignal("tck", Pins("tck", dir="i", assert_width=1)))
 120     io.append(Subsignal("tdo", Pins("tdo", dir="o", assert_width=1)))
 121     return Resource.family(*args, default_name="jtag", ios=io)
 122
 123 def UARTResource(*args, rx, tx):
 124     io = []
 125     io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
 126     io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
 127     return Resource.family(*args, default_name="uart", ios=io)
 128
 129
 130 def I2CResource(*args, scl, sda):
 131     ios = []
 132     pads = []
 133     pads.append(Subsignal("i", Pins(sda+"_i", dir="i", assert_width=1)))
 134     pads.append(Subsignal("o", Pins(sda+"_o", dir="o", assert_width=1)))
 135     pads.append(Subsignal("oe", Pins(sda+"_oe", dir="o", assert_width=1)))
 136     ios.append(Resource.family(sda, 0, default_name=sda, ios=pads))
 137     pads = []
 138     pads.append(Subsignal("i", Pins(scl+"_i", dir="i", assert_width=1)))
 139     pads.append(Subsignal("o", Pins(scl+"_o", dir="o", assert_width=1)))
 140     pads.append(Subsignal("oe", Pins(scl+"_oe", dir="o", assert_width=1)))
 141     ios.append(Resource.family(scl, 0, default_name=scl, ios=pads))
 142     return Resource.family(*args, default_name="i2c", ios=ios)
 143
 144
 145 # top-level demo module.
 146 class Blinker(Elaboratable):
 147     def __init__(self, pinset, resources, no_jtag_connect=False):
 148         self.no_jtag_connect = no_jtag_connect
 149         self.jtag = JTAG({}, "sync", resources=resources)
 150         #memory = Memory(width=32, depth=16)
 151         #self.sram = SRAM(memory=memory, bus=self.jtag.wb)
 152
 153     def elaborate(self, platform):
 154         jtag_resources = self.jtag.pad_mgr.resources
 155         m = Module()
 156         m.submodules.jtag = self.jtag
 157         #m.submodules.sram = self.sram
 158
 159         #count = Signal(5)
 160         #m.d.sync += count.eq(count+1)
 161         print ("resources", platform, jtag_resources.items())
 162         gpio = self.jtag.request('gpio')
 163         print (gpio, gpio.layout, gpio.fields)
 164         # get the GPIO bank, mess about with some of the pins
 165         #m.d.comb += gpio.gpio0.o.eq(1)
 166         #m.d.comb += gpio.gpio1.o.eq(gpio.gpio2.i)
 167         #m.d.comb += gpio.gpio1.oe.eq(count[4])
 168         #m.d.sync += count[0].eq(gpio.gpio1.i)
 169
 170         num_gpios = 4
 171         gpio_o_test = Signal(num_gpios)
 172         gpio_oe_test = Signal(num_gpios)
 173         # Wire up the output signal of each gpio by XOR'ing each bit of
 174         # gpio_o_test with gpio's input
 175         # Wire up each bit of gpio_oe_test signal to oe signal of each gpio.
 176         # Turn into a loop at some point, probably a way without
 177         # using get_attr()
 178         m.d.comb += gpio.gpio0.o.eq(gpio_o_test[0] ^ gpio.gpio0.i)
 179         m.d.comb += gpio.gpio1.o.eq(gpio_o_test[1] ^ gpio.gpio1.i)
 180         m.d.comb += gpio.gpio2.o.eq(gpio_o_test[2] ^ gpio.gpio2.i)
 181         m.d.comb += gpio.gpio3.o.eq(gpio_o_test[3] ^ gpio.gpio3.i)
 182
 183         m.d.comb += gpio.gpio0.oe.eq(gpio_oe_test[0])
 184         m.d.comb += gpio.gpio1.oe.eq(gpio_oe_test[1])
 185         m.d.comb += gpio.gpio2.oe.eq(gpio_oe_test[2])
 186         m.d.comb += gpio.gpio3.oe.eq(gpio_oe_test[3])
 187
 188         # get the UART resource, mess with the output tx
 189         uart = self.jtag.request('uart')
 190         print ("uart fields", uart, uart.fields)
 191         self.intermediary = Signal()
 192         m.d.comb += uart.tx.eq(self.intermediary)
 193         m.d.comb += self.intermediary.eq(uart.rx)
 194
 195         # to even be able to get at objects, you first have to make them
 196         # available - i.e. not as local variables
 197         self.gpio = gpio
 198         self.uart = uart
 199         self.gpio_o_test = gpio_o_test
 200         self.gpio_oe_test = gpio_oe_test
 201
 202         # sigh these wire up to the pads so you cannot set Signals
 203         # that are already wired
 204         if self.no_jtag_connect: # bypass jtag pad connect for testing purposes
 205             return m
 206         return self.jtag.boundary_elaborate(m, platform)
 207
 208     def ports(self):
 209         return list(self)
 210
 211     def __iter__(self):
 212         yield from self.jtag.iter_ports()
 213
 214 '''
 215     _trellis_command_templates = [
 216         r"""
 217         {{invoke_tool("yosys")}}
 218             {{quiet("-q")}}
 219             {{get_override("yosys_opts")|options}}
 220             -l {{name}}.rpt
 221             {{name}}.ys
 222         """,
 223     ]
 224 '''
 225
 226 # sigh, have to create a dummy platform for now.
 227 # TODO: investigate how the heck to get it to output ilang. or verilog.
 228 # or, anything, really.  but at least it doesn't barf
 229 class ASICPlatform(TemplatedPlatform):
 230     connectors = []
 231     resources = OrderedDict()
 232     required_tools = []
 233     command_templates = ['/bin/true'] # no command needed: stops barfing
 234     file_templates = {
 235         **TemplatedPlatform.build_script_templates,
 236         "{{name}}.il": r"""
 237             # {{autogenerated}}
 238             {{emit_rtlil()}}
 239         """,
 240         "{{name}}.debug.v": r"""
 241             /* {{autogenerated}} */
 242             {{emit_debug_verilog()}}
 243         """,
 244     }
 245     toolchain = None
 246     default_clk = "clk" # should be picked up / overridden by platform sys.clk
 247     default_rst = "rst" # should be picked up / overridden by platform sys.rst
 248
 249     def __init__(self, resources, jtag):
 250         self.jtag = jtag
 251         super().__init__()
 252
 253         # create set of pin resources based on the pinset, this is for the core
 254         #jtag_resources = self.jtag.pad_mgr.resources
 255         self.add_resources(resources)
 256
 257         # add JTAG without scan
 258         self.add_resources([JTAGResource('jtag', 0)], no_boundary_scan=True)
 259
 260     def add_resources(self, resources, no_boundary_scan=False):
 261         print ("ASICPlatform add_resources", resources)
 262         return super().add_resources(resources)
 263
 264     #def iter_ports(self):
 265     #    yield from super().iter_ports()
 266     #    for io in self.jtag.ios.values():
 267     #        print ("iter ports", io.layout, io)
 268     #        for field in io.core.fields:
 269     #            yield getattr(io.core, field)
 270     #        for field in io.pad.fields:
 271     #            yield getattr(io.pad, field)
 272
 273     # XXX these aren't strictly necessary right now but the next
 274     # phase is to add JTAG Boundary Scan so it maaay be worth adding?
 275     # at least for the print statements
 276     def get_input(self, pin, port, attrs, invert):
 277         self._check_feature("single-ended input", pin, attrs,
 278                             valid_xdrs=(0,), valid_attrs=None)
 279
 280         m = Module()
 281         print ("    get_input", pin, "port", port, port.layout)
 282         m.d.comb += pin.i.eq(self._invert_if(invert, port))
 283         return m
 284
 285     def get_output(self, pin, port, attrs, invert):
 286         self._check_feature("single-ended output", pin, attrs,
 287                             valid_xdrs=(0,), valid_attrs=None)
 288
 289         m = Module()
 290         print ("    get_output", pin, "port", port, port.layout)
 291         m.d.comb += port.eq(self._invert_if(invert, pin.o))
 292         return m
 293
 294     def get_tristate(self, pin, port, attrs, invert):
 295         self._check_feature("single-ended tristate", pin, attrs,
 296                             valid_xdrs=(0,), valid_attrs=None)
 297
 298         print ("    get_tristate", pin, "port", port, port.layout)
 299         m = Module()
 300         print ("       pad", pin, port, attrs)
 301         print ("       pin", pin.layout)
 302         return m
 303         #    m.submodules += Instance("$tribuf",
 304         #        p_WIDTH=pin.width,
 305         #        i_EN=pin.oe,
 306         #        i_A=self._invert_if(invert, pin.o),
 307         #        o_Y=port,
 308         #    )
 309         m.d.comb += io.core.o.eq(pin.o)
 310         m.d.comb += io.core.oe.eq(pin.oe)
 311         m.d.comb += pin.i.eq(io.core.i)
 312         m.d.comb += io.pad.i.eq(port.i)
 313         m.d.comb += port.o.eq(io.pad.o)
 314         m.d.comb += port.oe.eq(io.pad.oe)
 315         return m
 316
 317     def get_input_output(self, pin, port, attrs, invert):
 318         self._check_feature("single-ended input/output", pin, attrs,
 319                             valid_xdrs=(0,), valid_attrs=None)
 320
 321         print ("    get_input_output", pin, "port", port, port.layout)
 322         m = Module()
 323         print ("       port layout", port.layout)
 324         print ("       pin", pin)
 325         print ("            layout", pin.layout)
 326         #m.submodules += Instance("$tribuf",
 327         #    p_WIDTH=pin.width,
 328         #    i_EN=io.pad.oe,
 329         #    i_A=self._invert_if(invert, io.pad.o),
 330         #    o_Y=port,
 331         #)
 332         # Create aliases for the port sub-signals
 333         port_i = port.io[0]
 334         port_o = port.io[1]
 335         port_oe = port.io[2]
 336
 337         m.d.comb += pin.i.eq(self._invert_if(invert, port_i))
 338         m.d.comb += port_o.eq(self._invert_if(invert, pin.o))
 339         m.d.comb += port_oe.eq(pin.oe)
 340
 341         return m
 342
 343     def toolchain_prepare(self, fragment, name, **kwargs):
 344         """override toolchain_prepare in order to grab the fragment
 345         """
 346         self.fragment = fragment
 347         return super().toolchain_prepare(fragment, name, **kwargs)
 348
 349 """
 350 and to create a Platform instance with that list, and build
 351 something random
 352
 353    p=Platform()
 354    p.resources=listofstuff
 355    p.build(Blinker())
 356 """
 357 pinset = dummy_pinset()
 358 print(pinset)
 359 resources = create_resources(pinset)
 360 top = Blinker(pinset, resources, no_jtag_connect=False)#True)
 361
 362 vl = rtlil.convert(top, ports=top.ports())
 363 with open("test_jtag_blinker.il", "w") as f:
 364     f.write(vl)
 365
 366 if False:
 367     # XXX these modules are all being added *AFTER* the build process links
 368     # everything together.  the expectation that this would work is...
 369     # unrealistic.  ordering, clearly, is important.
 370
 371     # dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
 372     top.jtag.stop = False
 373     # rather than the client access the JTAG bus directly
 374     # create an alternative that the client sets
 375     class Dummy: pass
 376     cdut = Dummy()
 377     cdut.cbus = JTAGInterface()
 378
 379     # set up client-server on port 44843-something
 380     top.jtag.s = JTAGServer()
 381     cdut.c = JTAGClient()
 382     top.jtag.s.get_connection()
 383     #else:
 384     #    print ("running server only as requested, use openocd remote to test")
 385     #    sys.stdout.flush()
 386     #    top.jtag.s.get_connection(None) # block waiting for connection
 387
 388     # take copy of ir_width and scan_len
 389     cdut._ir_width = top.jtag._ir_width
 390     cdut.scan_len = top.jtag.scan_len
 391
 392     p = ASICPlatform (resources, top.jtag)
 393     p.build(top)
 394     # this is what needs to gets treated as "top", after "main module" top
 395     # is augmented with IO pads with JTAG tacked on.  the expectation that
 396     # the get_input() etc functions will be called magically by some other
 397     # function is unrealistic.
 398     top_fragment = p.fragment
 399
 400 # XXX simulating top (the module that does not itself contain IO pads
 401 # because that's covered by build) cannot possibly be expected to work
 402 # particularly when modules have been added *after* the platform build()
 403 # function has been called.
 404
 405 def test_case0():
 406     print("Starting sanity test case!")
 407     print("printing out list of stuff in top")
 408     print ("JTAG IOs", top.jtag.ios)
 409     # ok top now has a variable named "gpio", let's enumerate that too
 410     print("printing out list of stuff in top.gpio and its type")
 411     print(top.gpio.__class__.__name__, dir(top.gpio))
 412     # ok, it's a nmigen Record, therefore it has a layout.  let's print
 413     # that too
 414     print("top.gpio is a Record therefore has fields and a layout")
 415     print("    layout:", top.gpio.layout)
 416     print("    fields:", top.gpio.fields)
 417     print("Fun never ends...")
 418     print("    layout, gpio2:", top.gpio.layout['gpio2'])
 419     print("    fields, gpio2:", top.gpio.fields['gpio2'])
 420     print(top.jtag.__class__.__name__, dir(top.jtag))
 421     print("Pads:")
 422     print(top.jtag.resource_table_pads[('gpio', 0)])
 423
 424     # etc etc. you get the general idea
 425     delayVal = 0.2e-6
 426     yield top.uart.rx.eq(0)
 427     yield Delay(delayVal)
 428     yield Settle()
 429     yield top.gpio.gpio2.o.eq(0)
 430     yield top.gpio.gpio3.o.eq(1)
 431     yield
 432     yield top.gpio.gpio3.oe.eq(1)
 433     yield
 434     yield top.gpio.gpio3.oe.eq(0)
 435     # grab the JTAG resource pad
 436     gpios_pad = top.jtag.resource_table_pads[('gpio', 0)]
 437     yield gpios_pad.gpio3.i.eq(1)
 438     yield Delay(delayVal)
 439     yield Settle()
 440     yield top.gpio.gpio2.oe.eq(1)
 441     yield top.gpio.gpio3.oe.eq(1)
 442     yield gpios_pad.gpio3.i.eq(0)
 443     yield top.jtag.gpio.gpio2.i.eq(1)
 444     yield Delay(delayVal)
 445     yield Settle()
 446     gpio_o2 = 0
 447     for _ in range(20):
 448         # get a value first (as an integer).  you were trying to set
 449         # it to the actual Signal.  this is not going to work.  or if
 450         # it does, it's very scary.
 451         gpio_o2 = not gpio_o2
 452         yield top.gpio.gpio2.o.eq(gpio_o2)
 453
 454         # ditto: here you are trying to set to an AST expression
 455         # which is inadviseable (likely to fail)
 456         gpio_o3 = not gpio_o2
 457         yield top.gpio.gpio3.o.eq(gpio_o3)
 458         yield Delay(delayVal)
 459         yield Settle()
 460         # grab the JTAG resource pad
 461         uart_pad = top.jtag.resource_table_pads[('uart', 0)]
 462         yield uart_pad.rx.i.eq(gpio_o2)
 463         yield Delay(delayVal)
 464         yield Settle()
 465         yield # one clock cycle
 466         tx_val = yield uart_pad.tx.o
 467         print ("xmit uart", tx_val, gpio_o2)
 468
 469     print ("jtag pad table keys")
 470     print (top.jtag.resource_table_pads.keys())
 471     uart_pad = top.jtag.resource_table_pads[('uart', 0)]
 472     print ("uart pad", uart_pad)
 473     print ("uart pad", uart_pad.layout)
 474
 475     yield top.gpio.gpio2.oe.eq(0)
 476     yield top.gpio.gpio3.oe.eq(0)
 477     yield top.jtag.gpio.gpio2.i.eq(0)
 478     yield Delay(delayVal)
 479     yield Settle()
 480
 481 # Code borrowed from cesar, runs, but shouldn't actually work because of
 482 # self. statements and non-existent signal names.
 483 def test_case1():
 484     print("Example test case")
 485     yield Passive()
 486     while True:
 487         # Settle() is needed to give a quick response to
 488         # the zero delay case
 489         yield Settle()
 490         # wait for rel_o to become active
 491         while not (yield self.rel_o):
 492             yield
 493             yield Settle()
 494         # read the transaction parameters
 495         assert self.expecting, "an unexpected result was produced"
 496         delay = (yield self.delay)
 497         expected = (yield self.expected)
 498         # wait for `delay` cycles
 499         for _ in range(delay):
 500             yield
 501         # activate go_i for one cycle
 502         yield self.go_i.eq(1)
 503         yield self.count.eq(self.count + 1)
 504         yield
 505         # check received data against the expected value
 506         result = (yield self.port)
 507         assert result == expected,\
 508             f"expected {expected}, received {result}"
 509         yield self.go_i.eq(0)
 510         yield self.port.eq(0)
 511
 512 def test_gpios():
 513     print("Starting GPIO test case!")
 514     # Grab GPIO pad resource from JTAG BS
 515     print (top.jtag.boundary_scan_pads.keys())
 516     gpio0_o = top.jtag.boundary_scan_pads['gpio_0__gpio0__o']['o']
 517     gpio1_o = top.jtag.boundary_scan_pads['gpio_0__gpio1__o']['o']
 518
 519     # Have the sim run through a for-loop where the gpio_o_test is
 520     # incremented like a counter (0000, 0001...)
 521     # At each iteration of the for-loop, assert:
 522     # + output set at core matches output seen at pad
 523     # TODO + input set at pad matches input seen at core
 524     # TODO + if gpio_o_test bit is cleared, output seen at pad matches
 525     # input seen at pad
 526     num_gpio_o_states = top.gpio_o_test.width**2
 527     print("Num of permutations of gpio_o_test record: ", num_gpio_o_states)
 528     for gpio_o_val in range(0, num_gpio_o_states):
 529         yield top.gpio_o_test.eq(gpio_o_val)
 530         yield Settle()
 531         yield # Move to the next clk cycle
 532
 533         # yield the pad output
 534         pad0_out = yield gpio0_o
 535         pad1_out = yield gpio1_o
 536         print("gpio0", gpio0_o, bin(gpio_o_val), pad0_out, pad1_out)
 537         # gpio_o_val is a 4-bit binary number setting each pad (single-bit)
 538         assert ((gpio_o_val & 0b0001) != 0) == pad0_out
 539         assert ((gpio_o_val & 0b0010) != 0) == pad1_out
 540
 541     # Another for loop to run through gpio_oe_test. Assert:
 542     # + oe set at core matches oe seen at pad.
 543     # TODO
 544
 545 sim = Simulator(top)
 546 sim.add_clock(1e-6, domain="sync")      # standard clock
 547
 548 #sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server
 549 #if len(sys.argv) != 2 or sys.argv[1] != 'server':
 550 #sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester
 551 #sim.add_sync_process(wrap(dmi_sim(top.jtag)))  # handles (pretends to be) DMI
 552
 553 #sim.add_sync_process(wrap(test_case1()))
 554 #sim.add_sync_process(wrap(test_case0()))
 555 sim.add_sync_process(wrap(test_gpios()))
 556
 557 with sim.write_vcd("blinker_test.vcd"):
 558     sim.run()