src/spec/testing_stage1.py

   1 #!/usr/bin/env python3
   2 from nmigen.build.dsl import Resource, Subsignal, Pins
   3 from nmigen.build.plat import TemplatedPlatform
   4 from nmigen.build.res import ResourceManager, ResourceError
   5 from nmigen import Elaboratable, Signal, Module, Instance
   6 from collections import OrderedDict
   7 from jtag import JTAG, resiotypes
   8 from copy import deepcopy
   9
  10 # Was thinking of using these functions, but skipped for simplicity for now
  11 # XXX nope.  the output from JSON file.
  12 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
  13 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
  14 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
  15
  16 # File for stage 1 pinmux tested proposed by Luke,
  17 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
  18
  19
  20 def dummy_pinset():
  21     # sigh this needs to come from pinmux.
  22     gpios = []
  23     for i in range(4):
  24         gpios.append("%d*" % i)
  25     return {'uart': ['tx+', 'rx-'],
  26             'gpio': gpios,
  27             'i2c': ['sda*', 'scl+']}
  28
  29 """
  30 a function is needed which turns the results of dummy_pinset()
  31 into:
  32
  33 [UARTResource("uart", 0, tx=..., rx=..),
  34  I2CResource("i2c", 0, scl=..., sda=...),
  35  Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
  36  Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
  37  ...
  38 ]
  39 """
  40
  41
  42 def create_resources(pinset):
  43     resources = []
  44     for periph, pins in pinset.items():
  45         print(periph, pins)
  46         if periph == 'i2c':
  47             #print("I2C required!")
  48             resources.append(I2CResource('i2c', 0, sda='sda', scl='scl'))
  49         elif periph == 'uart':
  50             #print("UART required!")
  51             resources.append(UARTResource('uart', 0, tx='tx', rx='rx'))
  52         elif periph == 'gpio':
  53             #print("GPIO required!")
  54             print ("GPIO is defined as '*' type, meaning i, o and oe needed")
  55             ios = []
  56             for pin in pins:
  57                 pname = "gpio"+pin[:-1] # strip "*" on end
  58                 # urrrr... tristsate and io assume a single pin which is
  59                 # of course exactly what we don't want in an ASIC: we want
  60                 # *all three* pins but the damn port is not outputted
  61                 # as a triplet, it's a single Record named "io". sigh.
  62                 # therefore the only way to get a triplet of i/o/oe
  63                 # is to *actually* create explicit triple pins
  64                 pad = Subsignal("io",
  65                             Pins("%s_i %s_o %s_oe" % (pname, pname, pname),
  66                                  dir="io", assert_width=3))
  67                 ios.append(Resource(pname, 0, pad))
  68             resources.append(Resource.family(periph, 0, default_name="gpio",
  69                                              ios=ios))
  70
  71     # add clock and reset
  72     clk = Resource("clk", 0, Pins("sys_clk", dir="i"))
  73     rst = Resource("rst", 0, Pins("sys_rst", dir="i"))
  74     resources.append(clk)
  75     resources.append(rst)
  76     return resources
  77
  78
  79 def UARTResource(*args, rx, tx):
  80     io = []
  81     io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
  82     io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
  83     return Resource.family(*args, default_name="uart", ios=io)
  84
  85
  86 def I2CResource(*args, scl, sda):
  87     io = []
  88     io.append(Subsignal("scl", Pins(scl, dir="io", assert_width=1)))
  89     io.append(Subsignal("sda", Pins(sda, dir="io", assert_width=1)))
  90     return Resource.family(*args, default_name="i2c", ios=io)
  91
  92
  93 # ridiculously-simple top-level module.  doesn't even have a sync domain
  94 # and can't have one until a clock has been established by ASICPlatform.
  95 class Blinker(Elaboratable):
  96     def __init__(self, pinset):
  97         self.jtag = JTAG({}, "sync")
  98
  99     def elaborate(self, platform):
 100         m = Module()
 101         m.submodules.jtag = self.jtag
 102         count = Signal(5)
 103         m.d.sync += count.eq(5)
 104         print ("resources", platform.resources.items())
 105         gpio = platform.request('gpio')
 106         print (gpio, gpio.layout, gpio.fields)
 107         # get the GPIO bank, mess about with some of the pins
 108         m.d.comb += gpio.gpio0.io.o.eq(1)
 109         m.d.comb += gpio.gpio1.io.o.eq(gpio.gpio2.io.i)
 110         m.d.comb += gpio.gpio1.io.oe.eq(count[4])
 111         m.d.sync += count[0].eq(gpio.gpio1.io.i)
 112         # get the UART resource, mess with the output tx
 113         uart = platform.request('uart')
 114         print (uart, uart.fields)
 115         m.d.comb += uart.tx.eq(1)
 116         return m
 117
 118
 119 '''
 120     _trellis_command_templates = [
 121         r"""
 122         {{invoke_tool("yosys")}}
 123             {{quiet("-q")}}
 124             {{get_override("yosys_opts")|options}}
 125             -l {{name}}.rpt
 126             {{name}}.ys
 127         """,
 128     ]
 129 '''
 130
 131 # sigh, have to create a dummy platform for now.
 132 # TODO: investigate how the heck to get it to output ilang. or verilog.
 133 # or, anything, really.  but at least it doesn't barf
 134 class ASICPlatform(TemplatedPlatform):
 135     connectors = []
 136     resources = OrderedDict()
 137     required_tools = []
 138     command_templates = ['/bin/true']
 139     file_templates = {
 140         **TemplatedPlatform.build_script_templates,
 141         "{{name}}.il": r"""
 142             # {{autogenerated}}
 143             {{emit_rtlil()}}
 144         """,
 145         "{{name}}.debug.v": r"""
 146             /* {{autogenerated}} */
 147             {{emit_debug_verilog()}}
 148         """,
 149     }
 150     toolchain = None
 151     default_clk = "clk" # should be picked up / overridden by platform sys.clk
 152     default_rst = "rst" # should be picked up / overridden by platform sys.rst
 153
 154     def __init__(self, resources, jtag):
 155         self.pad_mgr = ResourceManager([], [])
 156         self.jtag = jtag
 157         super().__init__()
 158         # create set of pin resources based on the pinset, this is for the core
 159         self.add_resources(resources)
 160         # record resource lookup between core IO names and pads
 161         self.padlookup = {}
 162
 163     def request(self, name, number=0, *, dir=None, xdr=None):
 164         """request a Resource (e.g. name="uart", number=0) which will
 165         return a data structure containing Records of all the pins.
 166
 167         this override will also - automatically - create a JTAG Boundary Scan
 168         connection *without* any change to the actual Platform.request() API
 169         """
 170         # okaaaay, bit of shenanigens going on: the important data structure
 171         # here is Resourcemanager._ports.  requests add to _ports, which is
 172         # what needs redirecting.  therefore what has to happen is to
 173         # capture the number of ports *before* the request. sigh.
 174         start_ports = len(self._ports)
 175         value = super().request(name, number, dir=dir, xdr=xdr)
 176         end_ports = len(self._ports)
 177
 178         # now make a corresponding (duplicate) request to the pad manager
 179         # BUT, if it doesn't exist, don't sweat it: all it means is, the
 180         # application did not request Boundary Scan for that resource.
 181         pad_start_ports = len(self.pad_mgr._ports)
 182         try:
 183             pvalue = self.pad_mgr.request(name, number, dir=dir, xdr=xdr)
 184         except AssertionError:
 185             return value
 186         pad_end_ports = len(self.pad_mgr._ports)
 187
 188         # ok now we have the lengths: now create a lookup between the pad
 189         # and the core, so that JTAG boundary scan can be inserted in between
 190         core = self._ports[start_ports:end_ports]
 191         pads = self.pad_mgr._ports[pad_start_ports:pad_end_ports]
 192         # oops if not the same numbers added. it's a duplicate. shouldn't happen
 193         assert len(core) == len(pads), "argh, resource manager error"
 194         print ("core", core)
 195         print ("pads", pads)
 196
 197         # pad/core each return a list of tuples of (res, pin, port, attrs)
 198         for pad, core in zip(pads, core):
 199             # create a lookup on pin name to get at the hidden pad instance
 200             # this pin name will be handed to get_input, get_output etc.
 201             # and without the padlookup you can't find the (duplicate) pad.
 202             # note that self.padlookup and self.jtag.ios use the *exact* same
 203             # pin.name per pin
 204             pin = pad[1]
 205             corepin = core[1]
 206             if pin is None: continue # skip when pin is None
 207             assert corepin is not None # if pad was None, core should be too
 208             print ("iter", pad, pin.name)
 209             print ("existing pads", self.padlookup.keys())
 210             assert pin.name not in self.padlookup # no overwrites allowed!
 211             assert pin.name == corepin.name       # has to be the same!
 212             self.padlookup[pin.name] = pad        # store pad by pin name
 213
 214             # now add the IO Shift Register.  first identify the type
 215             # then request a JTAG IOConn. we can't wire it up (yet) because
 216             # we don't have a Module() instance. doh. that comes in get_input
 217             # and get_output etc. etc.
 218             iotype = resiotypes[pin.dir] # look up the C4M-JTAG IOType
 219             io = self.jtag.add_io(iotype=iotype, name=pin.name) # create IOConn
 220             self.jtag.ios[pin.name] = io # store IOConn Record by pin name
 221
 222         # finally return the value just like ResourceManager.request()
 223         return value
 224
 225     def add_resources(self, resources, no_boundary_scan=False):
 226         super().add_resources(resources)
 227         if no_boundary_scan:
 228             return
 229         # make a *second* - identical - set of pin resources for the IO ring
 230         padres = deepcopy(resources)
 231         self.pad_mgr.add_resources(padres)
 232
 233     # XXX these aren't strictly necessary right now but the next
 234     # phase is to add JTAG Boundary Scan so it maaay be worth adding?
 235     # at least for the print statements
 236     def get_input(self, pin, port, attrs, invert):
 237         self._check_feature("single-ended input", pin, attrs,
 238                             valid_xdrs=(0,), valid_attrs=None)
 239
 240         m = Module()
 241         print ("    get_input", pin, "port", port, port.layout)
 242         if pin.name in ['clk_0', 'rst_0']: # sigh
 243             # simple pass-through from port to pin
 244             print("No JTAG chain in-between")
 245             m.d.comb += pin.i.eq(self._invert_if(invert, port))
 246             return m
 247         (res, pin, port, attrs) = self.padlookup[pin.name]
 248         io = self.jtag.ios[pin.name]
 249         print ("       pad", res, pin, port, attrs)
 250         print ("       pin", pin.layout)
 251         print ("      jtag", io.core.layout, io.pad.layout)
 252         m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
 253         m.d.comb += pin.i.eq(io.core.i)
 254         return m
 255
 256     def get_output(self, pin, port, attrs, invert):
 257         self._check_feature("single-ended output", pin, attrs,
 258                             valid_xdrs=(0,), valid_attrs=None)
 259
 260         m = Module()
 261         print ("    get_output", pin, "port", port, port.layout)
 262         if pin.name in ['clk_0', 'rst_0']: # sigh
 263             # simple pass-through from pin to port
 264             print("No JTAG chain in-between")
 265             m.d.comb += port.eq(self._invert_if(invert, pin.o))
 266             return m
 267         (res, pin, port, attrs) = self.padlookup[pin.name]
 268         io = self.jtag.ios[pin.name]
 269         print ("       pad", res, pin, port, attrs)
 270         print ("       pin", pin.layout)
 271         print ("      jtag", io.core.layout, io.pad.layout)
 272         m.d.comb += port.eq(self._invert_if(invert, io.pad.o))
 273         m.d.comb += pin.o.eq(io.core.o)
 274         return m
 275
 276     def get_tristate(self, pin, port, attrs, invert):
 277         self._check_feature("single-ended tristate", pin, attrs,
 278                             valid_xdrs=(0,), valid_attrs=None)
 279
 280         print ("    get_tristate", pin, "port", port, port.layout)
 281         m = Module()
 282         if pin.name in ['clk_0', 'rst_0']: # sigh
 283             print("No JTAG chain in-between")
 284             # Can port's i/o/oe be accessed like this?
 285             m.d.comb += port.o.eq(pin.o)
 286             m.d.comb += port.oe.eq(pin.oe)
 287             m.d.comb += pin.i.eq(port.i)
 288             return m
 289         (res, pin, port, attrs) = self.padlookup[pin.name]
 290         io = self.jtag.ios[pin.name]
 291         print ("       pad", res, pin, port, attrs)
 292         print ("       pin", pin.layout)
 293         print ("      jtag", io.core.layout, io.pad.layout)
 294         m.d.comb += io.core.o.eq(pin.o)
 295         m.d.comb += io.core.oe.eq(pin.oe)
 296         m.d.comb += pin.i.eq(io.core.i)
 297         m.d.comb += io.pad.i.eq(port.i)
 298         m.d.comb += port.o.eq(io.pad.o)
 299         m.d.comb += port.oe.eq(io.pad.oe)
 300         return m
 301
 302     def get_input_output(self, pin, port, attrs, invert):
 303         self._check_feature("single-ended input/output", pin, attrs,
 304                             valid_xdrs=(0,), valid_attrs=None)
 305
 306         print ("    get_input_output", pin, "port", port, port.layout)
 307         m = Module()
 308         if pin.name in ['clk_0', 'rst_0']: # sigh
 309             print("No JTAG chain in-between")
 310             m.submodules += Instance("$tribuf",
 311                 p_WIDTH=pin.width,
 312                 i_EN=pin.oe,
 313                 i_A=self._invert_if(invert, pin.o),
 314                 o_Y=port,
 315             )
 316             m.d.comb += pin.i.eq(self._invert_if(invert, port))
 317             return m
 318         (res, pin, port, attrs) = self.padlookup[pin.name]
 319         io = self.jtag.ios[pin.name]
 320         print ("       pad", res, pin, port, attrs)
 321         print ("       pin", pin.layout)
 322         print ("      jtag", io.core.layout, io.pad.layout)
 323         m.submodules += Instance("$tribuf",
 324             p_WIDTH=pin.width,
 325             i_EN=io.pad.oe,
 326             i_A=self._invert_if(invert, io.pad.o),
 327             o_Y=port,
 328         )
 329         m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
 330         m.d.comb += pin.i.eq(io.core.i)
 331         m.d.comb += io.core.o.eq(pin.o)
 332         m.d.comb += io.core.oe.eq(pin.oe)
 333         return m
 334
 335
 336 """
 337 and to create a Platform instance with that list, and build
 338 something random
 339
 340    p=Platform()
 341    p.resources=listofstuff
 342    p.build(Blinker())
 343 """
 344 pinset = dummy_pinset()
 345 top = Blinker(pinset)
 346 print(pinset)
 347 resources = create_resources(pinset)
 348 p = ASICPlatform (resources, top.jtag)
 349 p.build(top)
 350