src/wire_def.py

   1 from params import *
   2 # == Intermediate wire definitions ==#
   3 muxwire = '''
   4       Wire#(Bit#({1}))   wrmux{0} <-mkDWire(0);'''
   5 generic_io = '''
   6       GenericIOType cell{0}_out=unpack(0);
   7       Wire#(Bit#(1)) cell{0}_in <-mkDWire(0);
   8 '''
   9 uartwires = '''
  10       Wire#(Bit#(1)) wruart{0}_rx <-mkDWire(0);
  11       Wire#(Bit#(1)) wruart{0}_tx <-mkDWire(0);
  12       GenericIOType uart{0}_rx_io=GenericIOType{{outputval:0, output_en:0,
  13                 input_en:1, pullup_en:0, pulldown_en:0, pushpull_en:0,
  14                 drivestrength:0, opendrain_en:0}};
  15       GenericIOType uart{0}_tx_io=GenericIOType{{outputval:wruart{0}_tx,
  16                 output_en:1, input_en:0, pullup_en:0, pulldown_en:0,
  17                 pushpull_en:0, drivestrength:0, opendrain_en:0}};
  18 '''
  19 spiwires = '''
  20       Wire#(Bit#(1)) wrspi{0}_sclk <-mkDWire(0);
  21       Wire#(Bit#(1)) wrspi{0}_mosi <-mkDWire(0);
  22       Wire#(Bit#(1)) wrspi{0}_ss   <-mkDWire(0);
  23       Wire#(Bit#(1)) wrspi{0}_miso <-mkDWire(0);
  24       GenericIOType spi{0}_sclk_io = GenericIOType{{outputval:wrspi{0}_sclk,
  25                 output_en:1, input_en:0, pullup_en:0, pulldown_en:0,
  26                 pushpull_en:0, drivestrength:0, opendrain_en:0}};
  27       GenericIOType spi{0}_mosi_io = GenericIOType{{outputval:wrspi{0}_mosi,
  28                 output_en:1, input_en:0, pullup_en:0, pulldown_en:0,
  29                 pushpull_en:0, drivestrength:0, opendrain_en:0}};
  30       GenericIOType spi{0}_ss_io = GenericIOType{{outputval:wrspi{0}_ss,
  31                 output_en:1, input_en:0, pullup_en:0, pulldown_en:0,
  32                 pushpull_en:0, drivestrength:0, opendrain_en:0}};
  33       GenericIOType spi{0}_miso_io = GenericIOType{{outputval:0, output_en:0,
  34                 input_en:1, pullup_en:0, pulldown_en:0, pushpull_en:0,
  35                 drivestrength:0, opendrain_en:0}};
  36
  37 '''
  38 twiwires = '''
  39       Wire#(Bit#(1)) wrtwi{0}_sda_out<-mkDWire(0);
  40       Wire#(Bit#(1)) wrtwi{0}_sda_outen<-mkDWire(0);
  41       Wire#(Bit#(1)) wrtwi{0}_sda_in<-mkDWire(0);
  42       Wire#(Bit#(1)) wrtwi{0}_scl_out<-mkDWire(0);
  43       Wire#(Bit#(1)) wrtwi{0}_scl_outen<-mkDWire(0);
  44       Wire#(Bit#(1)) wrtwi{0}_scl_in<-mkDWire(0);
  45       GenericIOType  twi{0}_sda_io = GenericIOType{{outputval:wrtwi{0}_sda_out,
  46                 output_en:wrtwi{0}_sda_outen, input_en:~wrtwi{0}_sda_outen,
  47                 pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0,
  48                 opendrain_en:0}};
  49       GenericIOType  twi{0}_scl_io = GenericIOType{{outputval:wrtwi{0}_scl_out,
  50                 output_en:wrtwi{0}_scl_outen, input_en:~wrtwi{0}_scl_outen,
  51                 pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0,
  52                 opendrain_en:0}};
  53 '''
  54 # =================================== #