src/wire_def.py

   1 # == Intermediate wire definitions ==#
   2 muxwire = '''
   3       Wire#(Bit#({1}))   wrmux{0} <-mkDWire(0);'''
   4 generic_io = '''
   5       GenericIOType cell{0}_out=unpack(0);
   6       Wire#(Bit#(1)) cell{0}_in <-mkDWire(0);
   7 '''
   8 uartwires = '''
   9       Wire#(Bit#(1)) wruart{0}_rx <-mkDWire(0);
  10       Wire#(Bit#(1)) wruart{0}_tx <-mkDWire(0);
  11       GenericIOType uart{0}_rx_io=GenericIOType{{outputval:0, output_en:0,
  12                 input_en:1, pullup_en:0, pulldown_en:0, pushpull_en:0,
  13                 drivestrength:0, opendrain_en:0}};
  14       GenericIOType uart{0}_tx_io=GenericIOType{{outputval:wruart{0}_tx,
  15                 output_en:1, input_en:0, pullup_en:0, pulldown_en:0,
  16                 pushpull_en:0, drivestrength:0, opendrain_en:0}};
  17 '''
  18 spiwires = '''
  19       Wire#(Bit#(1)) wrspi{0}_sclk <-mkDWire(0);
  20       Wire#(Bit#(1)) wrspi{0}_mosi <-mkDWire(0);
  21       Wire#(Bit#(1)) wrspi{0}_ss   <-mkDWire(0);
  22       Wire#(Bit#(1)) wrspi{0}_miso <-mkDWire(0);
  23       GenericIOType spi{0}_sclk_io = GenericIOType{{outputval:wrspi{0}_sclk,
  24                 output_en:1, input_en:0, pullup_en:0, pulldown_en:0,
  25                 pushpull_en:0, drivestrength:0, opendrain_en:0}};
  26       GenericIOType spi{0}_mosi_io = GenericIOType{{outputval:wrspi{0}_mosi,
  27                 output_en:1, input_en:0, pullup_en:0, pulldown_en:0,
  28                 pushpull_en:0, drivestrength:0, opendrain_en:0}};
  29       GenericIOType spi{0}_ss_io = GenericIOType{{outputval:wrspi{0}_ss,
  30                 output_en:1, input_en:0, pullup_en:0, pulldown_en:0,
  31                 pushpull_en:0, drivestrength:0, opendrain_en:0}};
  32       GenericIOType spi{0}_miso_io = GenericIOType{{outputval:0, output_en:0,
  33                 input_en:1, pullup_en:0, pulldown_en:0, pushpull_en:0,
  34                 drivestrength:0, opendrain_en:0}};
  35
  36 '''
  37 twiwires = '''
  38       Wire#(Bit#(1)) wrtwi{0}_sda_out<-mkDWire(0);
  39       Wire#(Bit#(1)) wrtwi{0}_sda_outen<-mkDWire(0);
  40       Wire#(Bit#(1)) wrtwi{0}_sda_in<-mkDWire(0);
  41       Wire#(Bit#(1)) wrtwi{0}_scl_out<-mkDWire(0);
  42       Wire#(Bit#(1)) wrtwi{0}_scl_outen<-mkDWire(0);
  43       Wire#(Bit#(1)) wrtwi{0}_scl_in<-mkDWire(0);
  44       GenericIOType  twi{0}_sda_io = GenericIOType{{outputval:wrtwi{0}_sda_out,
  45                 output_en:wrtwi{0}_sda_outen, input_en:~wrtwi{0}_sda_outen,
  46                 pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0,
  47                 opendrain_en:0}};
  48       GenericIOType  twi{0}_scl_io = GenericIOType{{outputval:wrtwi{0}_scl_out,
  49                 output_en:wrtwi{0}_scl_outen, input_en:~wrtwi{0}_scl_outen,
  50                 pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0,
  51                 opendrain_en:0}};
  52 '''
  53 # =================================== #