rename sys_clk to sys_pllclk - conflict with litex

[pinmux.git] / src / spec / pinfunctions.py

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index d30bc03d1f9ad204a0eb200f677409db4775da65..d93f82a9769d3b46241621b878ae9c4f6c766445 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -285,7 +285,7 @@ def vdd(suffix, bank):
     return (RangePin("-"), [], None)
 
 def sys(suffix, bank):
-    return (['CLK-',                       # incoming clock (to PLL)
+    return (['PLLCLK-',                       # incoming clock (to PLL)
              'PLLSELA0-', 'PLLSELA1-',     # PLL divider-selector
              'PLLTESTOUT+',                # divided-output (for testing)
              'PLLVCOUT+',                  # PLL VCO analog out (for testing)