AddingPeripherals.mdwn

diff --git a/docs/AddingPeripherals.mdwn b/docs/AddingPeripherals.mdwn
index e905a4a8c8043ad39cc79b9bfc147b76db70cc33..2ad2929505e2bc33ce92200be2876c63727aef8b 100644 (file)
--- a/docs/AddingPeripherals.mdwn
+++ b/docs/AddingPeripherals.mdwn
@@ -75,7 +75,7 @@ the address lines to 13-bit wide:
 
     def sdram3(suffix, bank):
         buspins = []
 
     def sdram3(suffix, bank):
         buspins = []

-        inout = [] 
+        inout = []

         for i in range(12, 13):
             buspins.append("SDRAD%d+" % i)
         for i in range(8, 64):
         for i in range(12, 13):
             buspins.append("SDRAD%d+" % i)
         for i in range(8, 64):


@@ -215,7 +215,7 @@ The first requirement is that the pins from the peripheral side be connected
 through to IO cells.  This can be verified by running the pinmux code
 generator (to activate "default" behaviour), just to see what happens:
 
 through to IO cells.  This can be verified by running the pinmux code
 generator (to activate "default" behaviour), just to see what happens:
 

-    $ python src/pinmux_generator.py -o i_class 
+    $ python src/pinmux_generator.py -o i_class

 
 Files are auto-generated in ./i\_class/bsv\_src and it is recommended
 to examine the pinmux.bsv file in an editor, and search for occurrences
 
 Files are auto-generated in ./i\_class/bsv\_src and it is recommended
 to examine the pinmux.bsv file in an editor, and search for occurrences


@@ -446,8 +446,6 @@ removed from the template:
         interface sdram_out=sdram.ifc_sdram_out;  <--- xxxx
     `endif                                        <--- xxxx
 
         interface sdram_out=sdram.ifc_sdram_out;  <--- xxxx
     `endif                                        <--- xxxx
 

-
-

 Next, again searching for signs of the "hand-written" code, we encounter
 the fabric connectivity, which wires the SDRAM to the AXI4.  We note however
 that there is not just one AXI slave device but *two*: one for the SDRAM
 Next, again searching for signs of the "hand-written" code, we encounter
 the fabric connectivity, which wires the SDRAM to the AXI4.  We note however
 that there is not just one AXI slave device but *two*: one for the SDRAM