autopep8 whitespace cleanup

diff --git a/src/spec/interfaces.py b/src/spec/interfaces.py
index 27b008fe33696a76f72a19af912cde9ab0dfa8eb..c354c8025cfdb86423cf2286f814983be605ec83 100644 (file)
--- a/src/spec/interfaces.py
+++ b/src/spec/interfaces.py
@@ -3,6 +3,7 @@
 from spec.pinfunctions import pinspec
 from copy import deepcopy
 
+
 def namesuffix(name, suffix, namelist):
     names = []
     for n in namelist:
@@ -21,6 +22,7 @@ class PinGen(object):
         in combination with setattr (below) gives the function a name
         in the Pinouts class, according to the pinspec.
     """
+
     def __init__(self, pinouts, fname, pinfn, bankspec):
         self.pinouts = pinouts
         self.bankspec = bankspec
@@ -34,9 +36,9 @@ class PinGen(object):
             prefix, pingroup = pingroup
         else:
             prefix = self.fname
-        if start and limit: # limit turns into an offset from start
+        if start and limit:  # limit turns into an offset from start
             limit = start + limit
-        pingroup = pingroup[start:limit] # see comment in spec.pinfunctions
+        pingroup = pingroup[start:limit]  # see comment in spec.pinfunctions
         pins = Pins(prefix, pingroup, self.bankspec,
                     suffix, offs, bank, mux,
                     spec, origsuffix=suffix)
@@ -44,6 +46,7 @@ class PinGen(object):
 
 # pinouts class
 
+
 class Pinouts(object):
     def __init__(self, bankspec):
         self.bankspec = bankspec
@@ -72,7 +75,7 @@ class Pinouts(object):
             for k in v:
                 assert k not in self.pins[pinidx], \
                     "pin %d position %d already taken\n%s\n%s" % \
-                        (pinidx, k, str(v), self.pins[pinidx])
+                    (pinidx, k, str(v), self.pins[pinidx])
             self.pins[pinidx].update(v)
 
     def keys(self):
@@ -110,7 +113,7 @@ class Pinouts(object):
             specname = fname + suffix
         else:
             specname = fname
-        #print "fname bank specname suffix ", fname, bank, specname, repr(
+        # print "fname bank specname suffix ", fname, bank, specname, repr(
         #    suffix)
         if specname in self.fnspec[fname]:
             # ok so some declarations may bring in different

diff --git a/src/spec/minitest.py b/src/spec/minitest.py
index febd9f096f971df24356ec5a5a1e91b92896578c..dc91d14a4151c6fc6ead305cbadea337c9173ea5 100644 (file)
--- a/src/spec/minitest.py
+++ b/src/spec/minitest.py
@@ -8,8 +8,8 @@ from spec.ifaceprint import display_fixed
 
 def pinspec():
     pinbanks = {
-                'B': 28,
-                }
+        'B': 28,
+    }
     bankspec = {}
     pkeys = sorted(pinbanks.keys())
     offs = 0
@@ -41,7 +41,6 @@ def pinspec():
     pinouts.uart("1", ('B', 2), "B", 2)
     pinouts.uart("2", ('B', 14), "B", 2)
 
-
     print ("""# Pinouts (PinMux)
 auto-generated by [[pinouts.py]]
 
@@ -118,7 +117,7 @@ auto-generated by [[pinouts.py]]
     # lists (interfaces, EINTs, PWMs) from available pins.
 
     minitest = ['ULPI0/8', 'ULPI1', 'MMC', 'SD0', 'UART0',
-              'TWI0', 'SPI0', 'B3:SD1', ]
+                'TWI0', 'SPI0', 'B3:SD1', ]
     minitest_eint = ['EINT_0', 'EINT_1', 'EINT_2', 'EINT_3', 'EINT_4']
     minitest_pwm = ['B2:PWM_0']
     descriptions = {
@@ -138,7 +137,6 @@ auto-generated by [[pinouts.py]]
                                   minitest, minitest_eint, minitest_pwm,
                                   descriptions)
 
-
     print ("""# Reference Datasheets
 
 datasheets and pinout links

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 9705e8c5d32c93e36fd426717d89280d5a2f646c..0a8d7bbadd5efb59af199eea7dd458ad56684959 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -27,51 +27,63 @@
     added).  see spec.interfaces.PinGen class slice on pingroup
 """
 
+
 def i2s(suffix, bank):
     return ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
 
+
 def emmc(suffix, bank):
     emmcpins = ['CMD+', 'CLK+']
     for i in range(8):
         emmcpins.append("D%d*" % i)
     return emmcpins
 
+
 def sdmmc(suffix, bank):
     sdmmcpins = ['CMD+', 'CLK+']
     for i in range(4):
         sdmmcpins.append("D%d*" % i)
     return sdmmcpins
 
+
 def spi(suffix, bank):
     return ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
 
+
 def quadspi(suffix, bank):
     return ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
 
+
 def i2c(suffix, bank):
     return ['SDA*', 'SCL*']
 
+
 def jtag(suffix, bank):
     return ['MS+', 'DI-', 'DO+', 'CK+']
 
+
 def uart(suffix, bank):
     return ['TX+', 'RX-']
 
+
 def ulpi(suffix, bank):
     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
     for i in range(8):
         ulpipins.append('D%d*' % i)
     return ulpipins
 
+
 def uartfull(suffix, bank):
     return ['TX+', 'RX-', 'CTS-', 'RTS+']
 
+
 def rgbttl(suffix, bank):
     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
     for i in range(24):
         ttlpins.append("D%d+" % i)
     return ttlpins
 
+
 def rgmii(suffix, bank):
     buspins = []
     for i in range(4):
@@ -84,6 +96,7 @@ def rgmii(suffix, bank):
                 'ECOL+', 'ETXERR+']
     return buspins
 
+
 def flexbus1(suffix, bank):
     buspins = []
     for i in range(8):
@@ -99,12 +112,14 @@ def flexbus1(suffix, bank):
         buspins.append("CS%d+" % i)
     return buspins
 
+
 def flexbus2(suffix, bank):
     buspins = []
     for i in range(8, 32):
         buspins.append("AD%d*" % i)
     return buspins
 
+
 def sdram1(suffix, bank):
     buspins = []
     for i in range(16):
@@ -123,6 +138,7 @@ def sdram1(suffix, bank):
                 'SDRRST+']
     return buspins
 
+
 def sdram2(suffix, bank):
     buspins = []
     for i in range(3, 6):
@@ -131,6 +147,7 @@ def sdram2(suffix, bank):
         buspins.append("SDRDQ%d*" % i)
     return buspins
 
+
 def mcu8080(suffix, bank):
     buspins = []
     for i in range(8):
@@ -145,6 +162,7 @@ def mcu8080(suffix, bank):
                 'MCURST+']
     return buspins
 
+
 class RangePin(object):
     def __init__(self, suffix, prefix=None):
         self.suffix = suffix
@@ -156,12 +174,15 @@ class RangePin(object):
             res.append("%s%d%s" % (self.prefix, idx, self.suffix))
         return res
 
+
 def eint(suffix, bank):
     return RangePin("*")
 
+
 def pwm(suffix, bank):
     return RangePin("+")
 
+
 def gpio(suffix, bank):
     return ("GPIO%s" % bank, RangePin(prefix=bank, suffix="*"))
 
@@ -187,5 +208,4 @@ pinspec = (('IIS', i2s),
            ('EINT', eint),
            ('PWM', pwm),
            ('GPIO', gpio),
-          )
-
+           )