projects
/
pinmux.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
e0eaa46
)
get access to jtag boundary scan pads for uart_0_tx/rx
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 6 Dec 2021 19:29:08 +0000
(19:29 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 6 Dec 2021 19:29:08 +0000
(19:29 +0000)
src/spec/testing_stage1.py
patch
|
blob
|
history
diff --git
a/src/spec/testing_stage1.py
b/src/spec/testing_stage1.py
index 6071b7073903563d9ec75938d82382ec7a8744ae..fe5143179b3139b50e199b76b980116486ca3408 100644
(file)
--- a/
src/spec/testing_stage1.py
+++ b/
src/spec/testing_stage1.py
@@
-579,21
+579,24
@@
def test_gpios():
def test_uart():
# grab the JTAG resource pad
def test_uart():
# grab the JTAG resource pad
- uart_pad = top.jtag.resource_table_pads[('uart', 0)]
- #uart_rx_pad = top.jtag.boundary_scan_pads['uart_0__rx__i']['i']
+ print ()
+ print ("bs pad keys", top.jtag.boundary_scan_pads.keys())
+ print ()
+ uart_rx_pad = top.jtag.boundary_scan_pads['uart_0__rx']['i']
+ uart_tx_pad = top.jtag.boundary_scan_pads['uart_0__tx']['o']
- print ("uart
pad", uart
_pad)
- print ("uart
pad", uart_pad.layout
)
+ print ("uart
rx pad", uart_rx
_pad)
+ print ("uart
tx pad", uart_tx_pad
)
# Test UART by writing 0 and 1 to RX
# Internally TX connected to RX,
# so match pad TX with RX
for i in range(0, 2):
# Test UART by writing 0 and 1 to RX
# Internally TX connected to RX,
# so match pad TX with RX
for i in range(0, 2):
- yield uart_
pad.rx.i
.eq(i)
+ yield uart_
rx_pad
.eq(i)
#yield uart_rx_pad.eq(i)
yield Settle()
yield # one clock cycle
#yield uart_rx_pad.eq(i)
yield Settle()
yield # one clock cycle
- tx_val = yield uart_
pad.tx.o
+ tx_val = yield uart_
tx_pad
print ("xmit uart", tx_val, 1)
assert tx_val == i
print ("xmit uart", tx_val, 1)
assert tx_val == i