add Makefile/lib auto-generator
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Apr 2018 08:33:11 +0000 (09:33 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Apr 2018 08:33:11 +0000 (09:33 +0100)
src/bsv/Makefile.template [new file with mode: 0644]
src/bsv/pinmux_generator.py

diff --git a/src/bsv/Makefile.template b/src/bsv/Makefile.template
new file mode 100644 (file)
index 0000000..d92dbc3
--- /dev/null
@@ -0,0 +1,40 @@
+### Makefile for the cclass project
+
+TOP_MODULE:=mkbus
+TOP_FILE:=bus.bsv
+TOP_DIR:=./
+WORKING_DIR := $(shell pwd)
+
+BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
+default: gen_verilog
+
+check-blue:
+       @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; 
+
+###### Setting the variables for bluespec compile #$############################
+BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules 
+BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires
+VERILOGDIR:=./verilog/
+BSVBUILDDIR:=./bsv_build/
+BSVOUTDIR:=./bin
+################################################################################
+
+########## BSIM COMPILE, LINK AND SIMULATE TARGETS ##########################
+.PHONY: check-restore
+check-restore:
+       @if [ "$(define_macros)" != "$(old_define_macros)" ];   then    make clean ;    fi;
+
+.PHONY: gen_verilog 
+gen_verilog: check-restore check-blue 
+       @echo Compiling mkTbSoc in Verilog for simulations ...
+       @mkdir -p $(BSVBUILDDIR); 
+       @mkdir -p $(VERILOGDIR); 
+       bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
+       @echo Compilation finished
+
+#############################################################################
+
+.PHONY: clean
+clean:
+       rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl*
+       rm -rf verilog obj_dir bsv_src
index c3fdc1cc131a67ef354ced747e6331dd9bdabf2b..5eeabf5eb4df6350ccd32bdf8812646e02faaa9b 100644 (file)
@@ -16,6 +16,7 @@
 # ========================================================================
 
 # default module imports
+import shutil
 import os
 import os.path
 import time
@@ -72,6 +73,19 @@ def pinmuxgen(pth=None, verify=True):
         bp = os.path.join(pth, bp)
     if not os.path.exists(bp):
         os.makedirs(bp)
+    bl = os.path.join(bp, 'bsv_lib')
+    if not os.path.exists(bl):
+        os.makedirs(bl)
+
+    cwd = os.path.split(__file__)[0]
+
+    # copy over template and library files
+    shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
+                os.path.join(bp, 'Makefile'))
+    cwd = os.path.join(cwd, 'bsv_lib')
+    for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
+        shutil.copyfile(os.path.join(cwd, fname),
+                    os.path.join(bl, fname))
 
     bus = os.path.join(bp, 'busenable.bsv')
     pmp = os.path.join(bp, 'pinmux.bsv')