AddingPeripherals.mdwn

diff --git a/docs/AddingPeripherals.mdwn b/docs/AddingPeripherals.mdwn
index 7f2faa59ef875c610def343421015a8d2f8f454f..c72337f7eaa39a1b10d07cbb2f7dee93e5f96b24 100644 (file)
--- a/docs/AddingPeripherals.mdwn
+++ b/docs/AddingPeripherals.mdwn
@@ -586,3 +586,42 @@ that drop sdram.axi4\_slave\_sdram and its associated cntrl reg from
 the soc\_template.bsv file.
 
 ## Connecting up the pins
+
+We are still not done!  It is however worth pointing out that if this peripheral
+were not wired into the pinmux, we would in fact be finished.  However there
+is a task that (previously having been left to outside tools) now needs to
+be specified, which is to connect the sdram's pins, declared in this
+instance in Ifc\_sdram\_out, and the PeripheralSideSDR instance that
+was kindly / strategically / thoughtfully / absolutely-necessarily exported
+from slow\_peripherals for exactly this purpose.
+
+Recall earlier that we took a cut/paste copy of the flexbus.py code.  If
+we now examine socgen.bsv we find that it contains connections to pins
+that match the FlexBus specification, not SDRAM.  So, returning to the
+declaration of the Ifc\_sdram\_out interface, we first identify the
+single-bit output-only pins, and add a mapping table between them:
+
+    class sdram(PBase):
+
+        def pinname_out(self, pname):
+            return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
+                    'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
+                    'sdrcke': 'ifc_sdram_out.osdr_cke',
+                    'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
+                    'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
+                    }.get(pname, '')
+
+Re-running the tool confirms that the relevant mkConnections are generated:
+
+    //sdr {'action': True, 'type': 'out', 'name': 'sdrcke'}
+    mkConnection(slow_peripherals.sdr0.sdrcke,
+                sdr0_sdrcke_sync.get);
+    mkConnection(sdr0_sdrcke_sync.put,
+                sdr0.ifc_sdram_out.osdr_cke);
+    //sdr {'action': True, 'type': 'out', 'name': 'sdrrasn'}
+    mkConnection(slow_peripherals.sdr0.sdrrasn,
+                sdr0_sdrrasn_sync.get);
+    mkConnection(sdr0_sdrrasn_sync.put,
+                sdr0.ifc_sdram_out.osdr_ras_n);
+
+Next, the multi-

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index 7002d6a4b73a8f257c8071ba318578cc0431cff5..79a9741f9f86a4b878baea62eaca750ae60f162d 100644 (file)
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -28,16 +28,12 @@ class sdram(PBase):
         return ["sdr{0}.axi4_slave_sdram",
                 "sdr{0}.axi4_slave_cntrl_reg"]
                 
-
-    def pinname_in(self, pname):
-        return {'ta': 'sdram_side.m_tAn',
-                }.get(pname, '')
-
     def pinname_out(self, pname):
-        return {'ale': 'sdram_side.m_ALE',
-                'oe': 'sdram_side.m_OEn',
-                'tbst': 'sdram_side.m_TBSTn',
-                'rw': 'sdram_side.m_R_Wn',
+        return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
+                'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
+                'sdrcke': 'ifc_sdram_out.osdr_cke',
+                'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
+                'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
                 }.get(pname, '')
 
     def _mk_clk_con(self, name, count, ctype):