add RG0 and RG1 to descripiton

diff --git a/src/spec/ls2.py b/src/spec/ls2.py
index f686db9748434ee62b9ad30453d3bc7d3d096e4a..7ed9f620f304a1e9bdc5a519d2a84bd6a976b06f 100644 (file)
--- a/src/spec/ls2.py
+++ b/src/spec/ls2.py
@@ -141,6 +141,7 @@ def pinspec():
             'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
              'VDD', 'VSS', 'SYS',
                 'MTWI', 'MSPI0',
+                'RG0', 'RG1',
                 # 'MSPI1', litex problem 25mar2021
                 'SDR']
     ls180_eint = []
@@ -153,6 +154,8 @@ def pinspec():
         'MSPI1': '',
         'UART0': '',
         'LPC1': '',
+        'RG0': '',
+        'RG1': '',
         'SYS': '',
         'LPC2': '',
         'SDR': '',