add axi fn_address_mapping

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index 33fcbe8e99a4a16e43c0c0ff399206c0b93e93cf..b97f257d275116692a0907d9c63e6af589016f7e 100644 (file)
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -58,16 +58,6 @@ package slow_peripherals;
        /*================================*/
 
        function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves))) fn_address_mapping (Bit#(`PADDR) addr);
-               `ifdef UART0
-                       if(addr>=`UART0Base && addr<=`UART0End)
-                               return tuple2(True,fromInteger(valueOf(Uart0_slave_num)));
-                       else
-               `endif
-               `ifdef UART1
-                       if(addr>=`UART1Base && addr<=`UART1End)
-                               return tuple2(True,fromInteger(valueOf(Uart1_slave_num)));
-                       else
-               `endif
                `ifdef CLINT
                        if(addr>=`ClintBase && addr<=`ClintEnd)
                                return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
@@ -78,46 +68,13 @@ package slow_peripherals;
                                return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
                        else
                `endif
-               `ifdef I2C0
-                       if(addr>=`I2C0Base && addr<=`I2C0End)   
-                               return tuple2(True,fromInteger(valueOf(I2c0_slave_num)));
-                       else
-               `endif
-               `ifdef I2C1
-                       if(addr>=`I2C1Base && addr<=`I2C1End)
-                               return tuple2(True,fromInteger(valueOf(I2c1_slave_num)));
-                       else
-               `endif
-               `ifdef QSPI0
-                       if(addr>=`QSPI0CfgBase && addr<=`QSPI0CfgEnd)
-                               return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
-                       else if(addr>=`QSPI0MemBase && addr<=`QSPI0MemEnd)
-                               return tuple2(True,fromInteger(valueOf(Qspi0_slave_num)));
-                       else
-               `endif
-               `ifdef QSPI1
-                       if(addr>=`QSPI1CfgBase && addr<=`QSPI1CfgEnd)
-                               return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
-                       else if(addr>=`QSPI1MemBase && addr<=`QSPI1MemEnd)
-                               return tuple2(True,fromInteger(valueOf(Qspi1_slave_num)));
-                       else
-               `endif
                `ifdef AXIEXP
                        if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
                                return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
                        else
                `endif
-    `ifdef PWM_AXI4Lite
-      if(addr>=`PWMBase && addr<=`PWMEnd)
-        return tuple2(True,fromInteger(valueOf(Pwm_slave_num)));
-      else
-    `endif
-
-    // NEEL EDIT 
-      // give slave number and adress map to whatever peripherals you instantiate on the AXI4_Lite
-      // slave.
-    // NEEL EDIT OVER
-               return tuple2(False,?);
+{4}
+                       return tuple2(False,?);
        endfunction
 
        (*synthesize*)

diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py
index 46342d0492f2876a37fadcbe54d8fcba8f936e7d..903cd3c8a0cec935917d785d4402f3ccb2ba97ff 100644 (file)
--- a/src/bsv/interface_decl.py
+++ b/src/bsv/interface_decl.py
@@ -279,6 +279,11 @@ class Interface(object):
             return ('', 0)
         return self.slow.axi_slave_idx(start, self.ifacename, count)
 
+    def axi_addr_map(self, count):
+        if not self.slow:
+            return ''
+        return self.slow.axi_addr_map(self.ifacename, count)
+
 
 class MuxInterface(Interface):
 
@@ -378,6 +383,13 @@ class Interfaces(InterfacesBase):
         decls = '\n'.join(list(filter(None, ret)))
         return axi_slave_declarations.format(decls)
 
+    def axi_addr_map(self, *args):
+        ret = []
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                ret.append(self.data[name].axi_addr_map(i))
+        return '\n'.join(list(filter(None, ret)))
+
 
 # ========= Interface declarations ================ #
 

diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index d609d34b465302d067df243d3e6665f41a91bf88..6f386b82c2f14e3f99ec621289ddce2ff50a6f0c 100644 (file)
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -20,9 +20,22 @@ class PBase(object):
                 "    `define%(bend)s  'h%(end)08X // %(comment)s" % locals(),
                 offs)
 
-    def axi_slave_idx(self, idx, name, ifacenum):
+    def axi_slave_name(self, name, ifacenum):
         name = name.upper()
-        return ("typedef {0} {1}{2}_slave_num;".format(idx, name, ifacenum), 1)
+        return "{0}{1}_slave_num".format(name, ifacenum)
+
+    def axi_slave_idx(self, idx, name, ifacenum):
+        name = self.axi_slave_name(name, ifacenum)
+        return ("typedef {0} {1};".format(idx, name), 1)
+
+    def axi_addr_map(self, name, ifacenum):
+        bname = self.axibase(name, ifacenum)
+        bend = self.axiend(name, ifacenum)
+        name = self.axi_slave_name(name, ifacenum)
+        return """\
+        if(addr>=`{0} && addr<=`{1})
+            return tuple2(True,fromInteger(valueOf({2})));
+        else""".format(bname, bend, name)
 
 
 class uart(PBase):

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 80988608f31c3b27331ff576b4dcf0d36a7c7106..abfb0bb276df0744ce85a667a15b93b8a2c61ce3 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -103,8 +103,10 @@ def write_slow(slow, template, p, ifaces):
     ifdecl = ifaces.slowifdecl()
     regdef = ifaces.axi_reg_def()
     slavedecl = ifaces.axi_slave_idx()
+    fnaddrmap = ifaces.axi_addr_map()
     with open(slow, "w") as bsv_file:
-        bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl))
+        bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
+                                       fnaddrmap))
 
 
 def write_bus(bus, p, ifaces):