add rst0 to sdram

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index 342a21d5bf608d99a5312a0e9c3ccdf8f92a559e..cd2fcefb7066beb3d48502d4d09aba337fbe83d9 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -110,7 +110,7 @@ package socgen;
     (*synthesize*)
     module mkSoc #(Bit#(`VADDR) reset_vector,
                  Clock slow_clock, Reset slow_reset, Clock uart_clock, 
-                 Reset uart_reset, Clock clk0, Clock tck, Reset trst
+                 Reset uart_reset, Clock clk0, Reset rst0, Clock tck, Reset trst
                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
         Reset core_reset <-exposeCurrentReset; // slow peripheral reset

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index ce6ba4364e43fd3492b531e64389c13434afa2fa..afc6908ede4b9fbac49f40397ade261c274511f4 100644 (file)
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -19,13 +19,13 @@ class sdram(PBase):
                 "Ifc_sdram_out sdr{0}_out;".format(count)
 
     def get_clk_spc(self, typ):
-        return "clk0, slow_reset"
+        return "clk0, rst0"
 
     def get_clock_reset(self, name, count):
         return "slow_clock, slow_reset"
 
     def mkfast_peripheral(self):
-        return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
+        return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0, rst0);"
 
     def _mk_connection(self, name=None, count=0):
         return ["sdr{0}.axi4_slave_sdram",