- ps.vss("E", ('W', 0), 0, 2, 1)
- ps.vdd("E", ('W', 1), 0, 2, 1)
- #ps.pwm("", ('W', 2), 0, 0, 2) comment out (litex problem 25mar2021)
- ps.eint("", ('W', 4), 0, 0, 3)
- #ps.mspi("1", ('W', 7), 0) comment out (litex problem 25mar2021)
- #ps.sdmmc("0", ('W', 11), 0) # comment out (litex problem 25mar2021)
- ps.vss("I", ('W', 30), 0, 4, 1)
- ps.vdd("I", ('W', 31), 0, 4, 1)
+ ps.vss("E", ('N', 0), 0, 2, 1)
+ ps.vdd("E", ('N', 1), 0, 2, 1)
+ ps.vdd("I", ('N', 2), 0, 12, 1)
+ ps.vss("I", ('N', 3), 0, 12, 1)
+ #ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021)
+ #ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021)
+ #ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021)
+ ps.sys("", ('N', 22), 0, 0, 6) # should be 6, to do all PLL pins
+ ps.vss("I", ('N', 28), 0, 11, 1)
+ ps.vdd("I", ('N', 29), 0, 11, 1)
+ ps.vss("I", ('N', 30), 0, 4, 1)
+ ps.vdd("I", ('N', 31), 0, 4, 1)