BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/plic
BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/pwm
BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/qspi
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/spi
BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/sdmmc
BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/uart
--- /dev/null
+from bsv.peripheral_gen.base import PBase
+
+
+class nspi(PBase):
+
+ def __init__(self, name):
+ PBase.__init__(self, name)
+ self.ifndict = {'N': name.upper(), 'n': name}
+
+ def slowimport(self):
+ return " import %(n)s :: *;" % self.ifndict
+
+ def slowifdecl(self):
+ return " interface %(N)s_out %(n)s{0}_out;\n" + \
+ " method Bit#(1) %(n)s{0}_isint;" % self.ifndict
+
+ def num_axi_regs32(self):
+ return 13
+
+ def mkslow_peripheral(self, size=0):
+ return " Ifc_%(n)s %(n)s{0} <- mk%(n)s();" % self.ifndict
+
+ def _mk_connection(self, name=None, count=0):
+ return "%(n)s{0}.slave" % self.ifndict
+
+ def pinname_out(self, pname):
+ return {'ck': 'out.clk_o',
+ 'nss': 'out.ncs_o',
+ }.get(pname, '')
+
+ def __disable_pinname_outen(self, pname):
+ return {'ck': 1,
+ 'nss': 1,
+ }.get(pname, '')
+
+ def mk_pincon(self, name, count):
+ ret = [PBase.mk_pincon(self, name, count)]
+ # special-case for gpio in, store in a temporary vector
+ plen = len(self.peripheral.pinspecs)
+ template = " mkConnection({0}.{1},\n\t\t\t{2}.{1});"
+ ps = "pinmux.peripheral_side.%s" % name
+ name = self.get_iname(count)
+ n = "{0}.out".format(name)
+ for ptype in ['io_out', 'io_out_en', 'io_in']:
+ ret.append(template.format(ps, ptype, n))
+ return '\n'.join(ret)
+
+ def num_irqs(self):
+ return 6
+
+ def plic_object(self, pname, idx):
+ return "{0}.interrupts()[{1}]".format(pname, idx)
+
+ def mk_ext_ifacedef(self, iname, inum):
+ name = self.get_iname(inum)
+ return " method {0}_isint = {0}.interrupts[5];".format(name)
+
+ def slowifdeclmux(self):
+ return " method Bit#(1) {1}{0}_isint;"
-from bsv.peripheral_gen.base import PBase
+from bsv.peripheral_gen.nspi import nspi
-
-class qspi(PBase):
-
- def slowimport(self):
- return " import qspi :: *;"
-
- def slowifdecl(self):
- return " interface QSPI_out qspi{0}_out;\n" + \
- " method Bit#(1) qspi{0}_isint;"
-
- def num_axi_regs32(self):
- return 13
-
- def mkslow_peripheral(self, size=0):
- return " Ifc_qspi qspi{0} <- mkqspi();"
-
- def _mk_connection(self, name=None, count=0):
- return "qspi{0}.slave"
-
- def pinname_out(self, pname):
- return {'ck': 'out.clk_o',
- 'nss': 'out.ncs_o',
- }.get(pname, '')
-
- def pinname_outen(self, pname):
- return {'ck': 1,
- 'nss': 1,
- }.get(pname, '')
-
- def mk_pincon(self, name, count):
- ret = [PBase.mk_pincon(self, name, count)]
- # special-case for gpio in, store in a temporary vector
- ret = []
- plen = len(self.peripheral.pinspecs)
- template = " mkConnection({0}.{1},\n\t\t\t{2}.{1});"
- ps = "pinmux.peripheral_side.%s" % name
- name = self.get_iname(count)
- n = "{0}.out".format(name)
- for ptype in ['io_out', 'io_out_en', 'io_in']:
- ret.append(template.format(ps, ptype, n))
- return '\n'.join(ret)
-
- def num_irqs(self):
- return 6
-
- def plic_object(self, pname, idx):
- return "{0}.interrupts()[{1}]".format(pname, idx)
-
- def mk_ext_ifacedef(self, iname, inum):
- name = self.get_iname(inum)
- return " method {0}_isint = {0}.interrupts[5];".format(name)
-
- def slowifdeclmux(self):
- return " method Bit#(1) {1}{0}_isint;"
+class qspi(nspi):
+ pass
-from bsv.peripheral_gen.base import PBase
+from bsv.peripheral_gen.nspi import nspi
-
-class spi(PBase):
-
- def slowimport(self):
- return " import qspi :: *;"
-
- def slowifdecl(self):
- return " interface QSPI_out spi{0}_out;\n" + \
- " method Bit#(1) spi{0}_isint;"
-
- def num_axi_regs32(self):
- return 13
-
- def mkslow_peripheral(self):
- return " Ifc_qspi spi{0} <- mkqspi();"
-
- def _mk_connection(self, name=None, count=0):
- return "spi{0}.slave"
-
- def pinname_out(self, pname):
- return {'clk': 'out.clk_o',
- 'nss': 'out.ncs_o',
- 'mosi': 'out.io_o[0]',
- 'miso': 'out.io_o[1]',
- }.get(pname, '')
-
- def pinname_outen(self, pname):
- return {'clk': 1,
- 'nss': 1,
- 'mosi': 'out.io_enable[0]',
- 'miso': 'out.io_enable[1]',
- }.get(pname, '')
-
- def mk_pincon(self, name, count):
- ret = [PBase.mk_pincon(self, name, count)]
- # special-case for gpio in, store in a temporary vector
- plen = len(self.peripheral.pinspecs)
- ret.append(" // XXX NSS and CLK are hard-coded master")
- ret.append(" // TODO: must add spi slave-mode")
- ret.append(" // all ins done in one rule from 4-bitfield")
- ret.append(" rule con_%s%d_io_in;" % (name, count))
- ret.append(" {0}{1}.out.io_i({{".format(name, count))
- for idx, pname in enumerate(['mosi', 'miso']):
- sname = self.peripheral.pname(pname).format(count)
- ps = "pinmux.peripheral_side.%s_in" % sname
- ret.append(" {0},".format(ps))
- ret.append(" 1'b0,1'b0")
- ret.append(" });")
- ret.append(" endrule")
- return '\n'.join(ret)
-
- def mk_ext_ifacedef(self, iname, inum):
- name = self.get_iname(inum)
- return " method {0}_isint = {0}.interrupts[5];".format(name)
-
- def slowifdeclmux(self):
- return " method Bit#(1) {1}{0}_isint;"
+class spi(nspi):
+ pass
return emmc(suffix, bank, pincount=4)
-def spi(suffix, bank):
- pins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
- return (pins, [])
-
-
-def quadspi(suffix, bank):
+def nspi(suffix, bank, iosize):
qpins = ['CK*', 'NSS*']
inout = []
- for i in range(4):
+ for i in range(iosize):
pname = "IO%d*" % i
qpins.append(pname)
inout.append(pname)
return (qpins, inout)
+def spi(suffix, bank):
+ return nspi(suffix, bank, 2)
+
+
+def quadspi(suffix, bank):
+ return nspi(suffix, bank, 4)
+
def i2c(suffix, bank):
return (['SDA*', 'SCL*'], [])
projects / pinmux.git / commitdiff