git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Andrew Waterman <waterman@cs.berkeley.edu>
	Fri, 26 Jul 2013 10:34:51 +0000 (03:34 -0700)
committer	Andrew Waterman <waterman@cs.berkeley.edu>
	Fri, 26 Jul 2013 10:34:51 +0000 (03:34 -0700)
commit	0de1489e8ab4a527fbcb1440a8fd5b2d4c8c9260
tree	af8831954cb5a8b5d42aae8bed76a2a9b1a114c9	tree
parent	d237ebbd5c7a68443ec94c0127e98071b59399b0	commit \| diff

Generate instruction decoder dynamically

This will make it easier for accelerators to add instructions.

12 files changed:

Simple-V augmented version of spike