git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Andrew Waterman <waterman@cs.berkeley.edu>
	Thu, 26 Mar 2015 07:28:10 +0000 (00:28 -0700)
committer	Andrew Waterman <waterman@cs.berkeley.edu>
	Fri, 27 Mar 2015 02:26:32 +0000 (19:26 -0700)
commit	180554d8f20e6ed5d90790579b85535c890ebc68
tree	f7ab03177e697be2264bc0ab2a5ca2bf546eedfb	tree
parent	41fa048e935d6e95d50dcb8bb463658b7a4d718e	commit \| diff

Serialize counters without throwing C++ exceptions

Ideally, a similar mechanism will apply to target machine exceptions.

Simple-V augmented version of spike