git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Tim Newsome <tim@sifive.com>
	Tue, 26 Apr 2016 21:32:08 +0000 (14:32 -0700)
committer	Tim Newsome <tim@sifive.com>
	Mon, 23 May 2016 19:12:11 +0000 (12:12 -0700)
commit	7baa7795ba6b878f1dc859f4d4ee239bb569c750
tree	146a42f110714fdd750381df3c8d1a94fa1c17f1	tree
parent	ffe4998fe57c5e58e591fc75e62e092e8e20d668	commit \| diff

gdb can attach and read the PC:

(gdb) target remote localhost:1234
Remote debugging using localhost:1234
0x0000000000010178 in fib (n=0) at waste.c:1
1 unsigned int fib(unsigned int n) {
(gdb)

riscv/execute.cc		diff \| blob \| history
riscv/gdbserver.cc		diff \| blob \| history
riscv/gdbserver.h		diff \| blob \| history
riscv/mmu.h		diff \| blob \| history

Simple-V augmented version of spike

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