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(parent: d2e9a10) | patch
C.LWSP and C.LDSP with rd=0 are legal instructions
authorAndrew Waterman <andrew@sifive.com>
Fri, 4 May 2018 00:14:28 +0000 (17:14 -0700)
committerAndrew Waterman <andrew@sifive.com>
Fri, 4 May 2018 00:14:28 +0000 (17:14 -0700)
commitd336aee08ba9c5715d5d7836a39003e62ee4ada8
treee9c02e1b420ad64f91a85118495a80352ec1413etree
parentd2e9a109e8f7b851fd153b469cc42a8519d85679commit | diff
C.LWSP and C.LDSP with rd=0 are legal instructions

This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982
riscv/insns/c_flwsp.h diff | blob | history
riscv/insns/c_lwsp.h diff | blob | history
Simple-V augmented version of spike