| 2018-10-10 |
Luke Kenneth... | add operators library to contain operator-overloads... |
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| 2018-10-09 |
Luke Kenneth... | get predicated-vectorised branch working |
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| 2018-10-09 |
Luke Kenneth... | save branch address and predication merged result,... |
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| 2018-10-09 |
Luke Kenneth... | add explanatory comment |
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| 2018-10-09 |
Luke Kenneth... | add explanatory comment |
commit | commitdiff | tree |
| 2018-10-09 |
Luke Kenneth... | start adding explicit twin-predicated branch identifica... |
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| 2018-10-09 |
Luke Kenneth... | extend sv register file from 64 to 128 after discussion. |
commit | commitdiff | tree |
| 2018-10-07 |
Luke Kenneth... | override setpc macro so that sv can redirect it in... |
commit | commitdiff | tree |
| 2018-10-07 |
Luke Kenneth... | swap #ifdef USING_NOREGS so that it is possible to... |
commit | commitdiff | tree |
| 2018-10-07 |
Luke Kenneth... | add rd bit-setting function |
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| 2018-10-07 |
Luke Kenneth... | add extra debug printing for c.lwsp |
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| 2018-10-07 |
Luke Kenneth... | add rvc_swsp_imm sv overload, provides vector unit... |
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| 2018-10-06 |
Luke Kenneth... | c.swsp and c.fswsp predication and offset enabling |
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| 2018-10-06 |
Luke Kenneth... | allow x2 (sp) to be redirected in C.LWSP |
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| 2018-10-06 |
Luke Kenneth... | temporary hack disabling SV in anything other than... |
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| 2018-10-06 |
Luke Kenneth... | whoops inverted ldsp and lwsp immediates |
commit | commitdiff | tree |
| 2018-10-06 |
Luke Kenneth... | create ldsp immediate offset overrides |
commit | commitdiff | tree |
| 2018-10-06 |
Luke Kenneth... | add in predication for immediate, for C.LWSP |
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| 2018-10-05 |
Luke Kenneth... | reorganise src and dest vector-element offsets |
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| 2018-10-05 |
Luke Kenneth... | add srcoffs and destoffs sv state, alter CSRs |
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| 2018-10-04 |
Luke Kenneth... | reorganise twin-predication |
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| 2018-10-04 |
Luke Kenneth... | big reorganisation to support twin-predication |
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| 2018-10-03 |
Luke Kenneth... | add in twin-predication identification |
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| 2018-10-03 |
Luke Kenneth... | decided not to change the behaviour of LOAD/STORE |
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| 2018-10-02 |
Luke Kenneth... | start work on parallelsing LOAD, pass in parameter... |
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| 2018-10-02 |
Luke Kenneth... | debug print for floating-point regs |
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| 2018-10-01 |
Luke Kenneth... | add comment explaining why invert isnt done in zeroing... |
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| 2018-10-01 |
Luke Kenneth... | add comment explaining use of insn._rd() in zeroing |
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| 2018-10-01 |
Luke Kenneth... | whoops vloop continuation logic the wrong way round |
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| 2018-10-01 |
Luke Kenneth... | skip parallelisation of complex LR/SC operations |
commit | commitdiff | tree |
| 2018-10-01 |
Luke Kenneth... | identify type of instruction with additional #defines |
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth... | add a #define to id_regs.py which indicates name of... |
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| 2018-09-30 |
Luke Kenneth... | list of instructions to avoid parallelising |
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| 2018-09-30 |
Luke Kenneth... | update template comment |
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| 2018-09-30 |
Luke Kenneth... | lots of debugging of predication, found other errors |
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth... | add sv support for zeroing predication in dest register |
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth... | add in predication to sv instruction execution |
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth... | start linking in predication into sv |
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth... | use an alternative logic for detecting scalar / loop-end |
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth... | add compressed-identifying patterns to id_regs.py |
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth... | fix code template for when SPIKE_SIMPLEV is not defined |
commit | commitdiff | tree |
| 2018-09-30 |
Luke Kenneth... | yuk. break id_regs.py being a generic tool by skipping... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | fix bug in sv template where FRS2 was checking rs3 |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add checks for RVC registers to sv template |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add sv_insn_t overloads for rvc registers |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | also arrange for id_regs.py to identify compressed... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | a LOT of debugging and fixing, sv loop actually working |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | move SV CSRs to user-read-write |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add near-duplicate of SV CFG REG CSRs, for predication |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add implementation of CSR SV CFG regs 0-7 |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | assign SV REG CSRs (using new union ability) |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | make sv csr tables a union so they can be assigned... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add support for CSR_SVVL to CSRRWI as well |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | fix bug in CSR set SVVL: val has already been looked up |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add stub for SV REG configs |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | stop a compiler warning |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | reorganise from moving sv_pred_* and sv_reg_* tables... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | have to move SV CSRs into processor_t |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | add 8 CSRs for registers and predication each |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | whoops dont need separate SVSETVL/SVGETVL CSRs |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | revert addition of svsetvl as an actual opcode, add... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | Revert "sv setvl as a csr not going to work, add getvl... |
commit | commitdiff | tree |
| 2018-09-29 |
Luke Kenneth... | Revert "manually add svsetvl instruction" |
commit | commitdiff | tree |
| 2018-09-28 |
Luke Kenneth... | manually add svsetvl instruction |
commit | commitdiff | tree |
| 2018-09-28 |
Luke Kenneth... | sv setvl as a csr not going to work, add getvl only |
commit | commitdiff | tree |
| 2018-09-27 |
Luke Kenneth... | adding sv vector length CSR to processor state, and... |
commit | commitdiff | tree |
| 2018-09-27 |
Luke Kenneth... | add sv predication function |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | save some cpu cycles by |ing the checks for vectorop... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | whoops vectorop has to be |= not &= to accumulate ... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | cache the sv redirected register values on each loop |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | remembered that the use of sv registers have to be... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | clarify comments on (key strategic) sv_insn_t::remap... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | actually implement sv register re-mapping |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | ok this is tricky: an extra parameter has to be passed... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | move sv remap function to sv.cc (not inline) |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | check if register redirection is active, and if vectori... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | comment why sv_insn_t is set up the way it is; add... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | easier to #define USING_NOREGS if the opcode does not... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | include auto-generated identification of use of registe... |
commit | commitdiff | tree |
| 2018-09-26 |
Luke Kenneth... | shuffle things around a bit for sv, put rv32/64_name... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | skip id_reg.py parsing its own output; stop outputting... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | change to instruction template parsing, create one... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | add decode.h header to sv.h |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | rename sv vlen to sv voffs, add csr and reg tables |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | add reference to vector length in sv |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | use sv_insn_t class in instruction template |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | add sv_insn_t class (inherits from insn_t) |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | argh cant virtualise rd/rs1-3, due to union usage with... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | sv: rd, rs1/2/3 become virtual so that sv_insn_t can... |
commit | commitdiff | tree |
| 2018-09-25 |
Luke Kenneth... | clarify sv cam table |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | define CSR and register tables for SV |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | remove unneeded use of AM_CONDITIONAL |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | add #define for SPIKE_SIMPLEV, re-run autoreconf |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | create #defines from identified registers, per opcode |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | clarify docstring on id_regs.py |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | add function identifying the registers in each emulated... |
commit | commitdiff | tree |
| 2018-09-24 |
Luke Kenneth... | identify instructions, plan: extract registers |
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| 2018-09-13 |
Andrew Waterman | Update README master |
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| 2018-09-06 |
Tim Newsome | Merge pull request #235 from riscv/sba |
commit | commitdiff | tree |
| 2018-09-05 |
Tim Newsome | Fix cut-and-paste bug in 64-bit SBA loads. |
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