13 from testlib
import assertEqual
, assertNotEqual
, assertIn
, assertNotIn
14 from testlib
import assertGreater
, assertRegexpMatches
, assertLess
15 from testlib
import GdbTest
, GdbSingleHartTest
, TestFailed
, assertTrue
17 MSTATUS_UIE
= 0x00000001
18 MSTATUS_SIE
= 0x00000002
19 MSTATUS_HIE
= 0x00000004
20 MSTATUS_MIE
= 0x00000008
21 MSTATUS_UPIE
= 0x00000010
22 MSTATUS_SPIE
= 0x00000020
23 MSTATUS_HPIE
= 0x00000040
24 MSTATUS_MPIE
= 0x00000080
25 MSTATUS_SPP
= 0x00000100
26 MSTATUS_HPP
= 0x00000600
27 MSTATUS_MPP
= 0x00001800
28 MSTATUS_FS
= 0x00006000
29 MSTATUS_XS
= 0x00018000
30 MSTATUS_MPRV
= 0x00020000
31 MSTATUS_PUM
= 0x00040000
32 MSTATUS_MXR
= 0x00080000
33 MSTATUS_VM
= 0x1F000000
34 MSTATUS32_SD
= 0x80000000
35 MSTATUS64_SD
= 0x8000000000000000
37 # pylint: disable=abstract-method
39 def ihex_line(address
, record_type
, data
):
40 assert len(data
) < 128
41 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
43 check
+= address
% 256
49 line
+= "%02X" % value
50 line
+= "%02X\n" % ((256-check
)%256)
54 assert line
.startswith(":")
56 data_len
= int(line
[:2], 16)
57 address
= int(line
[2:6], 16)
58 record_type
= int(line
[6:8], 16)
60 for i
in range(data_len
):
61 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
62 return record_type
, address
, data
64 def readable_binary_string(s
):
65 return "".join("%02x" % ord(c
) for c
in s
)
67 class SimpleRegisterTest(GdbTest
):
68 def check_reg(self
, name
, alias
):
69 a
= random
.randrange(1<<self
.hart
.xlen
)
70 b
= random
.randrange(1<<self
.hart
.xlen
)
71 self
.gdb
.p("$%s=0x%x" % (name
, a
))
72 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
74 assertEqual(self
.gdb
.p("$%s" % name
), a
)
75 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
76 self
.gdb
.p("$%s=0x%x" % (alias
, b
))
77 assertEqual(self
.gdb
.p("$%s" % name
), b
)
79 assertEqual(self
.gdb
.p("$%s" % name
), b
)
80 assertEqual(self
.gdb
.p("$%s" % alias
), b
)
84 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
85 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
86 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
87 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 12))
88 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 16))
89 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
91 class SimpleS0Test(SimpleRegisterTest
):
93 self
.check_reg("s0", "x8")
95 class SimpleS1Test(SimpleRegisterTest
):
97 self
.check_reg("s1", "x9")
99 class SimpleT0Test(SimpleRegisterTest
):
101 self
.check_reg("t0", "x5")
103 class SimpleT1Test(SimpleRegisterTest
):
105 self
.check_reg("t1", "x6")
107 class SimpleF18Test(SimpleRegisterTest
):
108 def check_reg(self
, name
, alias
):
109 if self
.hart
.extensionSupported('F'):
110 self
.gdb
.p_raw("$mstatus=$mstatus | 0x00006000")
114 self
.gdb
.p_raw("$%s=%f" % (name
, a
))
115 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
117 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - a
), .001)
118 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
119 self
.gdb
.p_raw("$%s=%f" % (alias
, b
))
120 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
122 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
123 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - b
), .001)
125 output
= self
.gdb
.p_raw("$" + name
)
126 assertEqual(output
, "void")
127 output
= self
.gdb
.p_raw("$" + alias
)
128 assertEqual(output
, "void")
131 self
.check_reg("f18", "fs2")
133 class SimpleMemoryTest(GdbTest
):
134 def access_test(self
, size
, data_type
):
135 assertEqual(self
.gdb
.p("sizeof(%s)" % data_type
), size
)
136 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
137 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
138 addrA
= self
.hart
.ram
139 addrB
= self
.hart
.ram
+ self
.hart
.ram_size
- size
140 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrA
, a
))
141 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrB
, b
))
142 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrA
)), a
)
143 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrB
)), b
)
145 class MemTest8(SimpleMemoryTest
):
147 self
.access_test(1, 'char')
149 class MemTest16(SimpleMemoryTest
):
151 self
.access_test(2, 'short')
153 class MemTest32(SimpleMemoryTest
):
155 self
.access_test(4, 'int')
157 class MemTest64(SimpleMemoryTest
):
159 self
.access_test(8, 'long long')
161 # FIXME: I'm not passing back invalid addresses correctly in read/write memory.
162 #class MemTestReadInvalid(SimpleMemoryTest):
164 # # This test relies on 'gdb_report_data_abort enable' being executed in
165 # # the openocd.cfg file.
167 # self.gdb.p("*((int*)0xdeadbeef)")
168 # assert False, "Read should have failed."
169 # except testlib.CannotAccess as e:
170 # assertEqual(e.address, 0xdeadbeef)
171 # self.gdb.p("*((int*)0x%x)" % self.hart.ram)
173 #class MemTestWriteInvalid(SimpleMemoryTest):
175 # # This test relies on 'gdb_report_data_abort enable' being executed in
176 # # the openocd.cfg file.
178 # self.gdb.p("*((int*)0xdeadbeef)=8675309")
179 # assert False, "Write should have failed."
180 # except testlib.CannotAccess as e:
181 # assertEqual(e.address, 0xdeadbeef)
182 # self.gdb.p("*((int*)0x%x)=6874742" % self.hart.ram)
184 class MemTestBlock(GdbTest
):
189 a
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
191 for i
in range(self
.length
/ self
.line_length
):
192 line_data
= "".join(["%c" % random
.randrange(256)
193 for _
in range(self
.line_length
)])
195 a
.write(ihex_line(i
* self
.line_length
, 0, line_data
))
198 self
.gdb
.command("shell cat %s" % a
.name
)
199 self
.gdb
.command("restore %s 0x%x" % (a
.name
, self
.hart
.ram
))
201 for offset
in range(0, self
.length
, increment
) + [self
.length
-4]:
202 value
= self
.gdb
.p("*((int*)0x%x)" % (self
.hart
.ram
+ offset
))
203 written
= ord(data
[offset
]) | \
204 (ord(data
[offset
+1]) << 8) | \
205 (ord(data
[offset
+2]) << 16) | \
206 (ord(data
[offset
+3]) << 24)
207 assertEqual(value
, written
)
209 b
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
210 self
.gdb
.command("dump ihex memory %s 0x%x 0x%x" % (b
.name
,
211 self
.hart
.ram
, self
.hart
.ram
+ self
.length
))
212 self
.gdb
.command("shell cat %s" % b
.name
)
213 for line
in b
.xreadlines():
214 record_type
, address
, line_data
= ihex_parse(line
)
216 written_data
= data
[address
:address
+len(line_data
)]
217 if line_data
!= written_data
:
219 "Data mismatch at 0x%x; wrote %s but read %s" % (
220 address
, readable_binary_string(written_data
),
221 readable_binary_string(line_data
)))
223 class InstantHaltTest(GdbTest
):
225 """Assert that reset is really resetting what it should."""
226 self
.gdb
.command("monitor reset halt")
227 self
.gdb
.command("flushregs")
228 threads
= self
.gdb
.threads()
232 pcs
.append(self
.gdb
.p("$pc"))
234 assertIn(pc
, self
.hart
.reset_vectors
)
235 # mcycle and minstret have no defined reset value.
236 mstatus
= self
.gdb
.p("$mstatus")
237 assertEqual(mstatus
& (MSTATUS_MIE | MSTATUS_MPRV |
240 class InstantChangePc(GdbTest
):
242 """Change the PC right as we come out of reset."""
244 self
.gdb
.command("monitor reset halt")
245 self
.gdb
.command("flushregs")
246 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
247 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
248 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
249 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
251 assertEqual((self
.hart
.ram
+ 4), self
.gdb
.p("$pc"))
253 assertEqual((self
.hart
.ram
+ 8), self
.gdb
.p("$pc"))
255 class DebugTest(GdbSingleHartTest
):
256 # Include malloc so that gdb can make function calls. I suspect this malloc
257 # will silently blow through the memory set aside for it, so be careful.
258 compile_args
= ("programs/debug.c", "programs/checksum.c",
259 "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
265 def exit(self
, expected_result
=0xc86455d4):
266 output
= self
.gdb
.c()
267 assertIn("Breakpoint", output
)
268 assertIn("_exit", output
)
269 assertEqual(self
.gdb
.p("status"), expected_result
)
271 class DebugCompareSections(DebugTest
):
273 output
= self
.gdb
.command("compare-sections")
275 for line
in output
.splitlines():
276 if line
.startswith("Section"):
277 assert line
.endswith("matched.")
279 assertGreater(matched
, 1)
281 class DebugFunctionCall(DebugTest
):
283 self
.gdb
.b("main:start")
285 assertEqual(self
.gdb
.p('fib(6)'), 8)
286 assertEqual(self
.gdb
.p('fib(7)'), 13)
289 class DebugChangeString(DebugTest
):
291 text
= "This little piggy went to the market."
292 self
.gdb
.b("main:start")
294 self
.gdb
.p('fox = "%s"' % text
)
295 self
.exit(0x43b497b8)
297 class DebugTurbostep(DebugTest
):
299 """Single step a bunch of times."""
300 self
.gdb
.b("main:start")
302 self
.gdb
.command("p i=0")
308 pc
= self
.gdb
.p("$pc")
309 assertNotEqual(last_pc
, pc
)
310 if last_pc
and pc
> last_pc
and pc
- last_pc
<= 4:
315 # Some basic sanity that we're not running between breakpoints or
317 assertGreater(jumps
, 1)
318 assertGreater(advances
, 5)
320 class DebugExit(DebugTest
):
324 class DebugSymbols(DebugTest
):
328 output
= self
.gdb
.c()
329 assertIn(", main ", output
)
330 output
= self
.gdb
.c()
331 assertIn(", rot13 ", output
)
333 class DebugBreakpoint(DebugTest
):
336 # The breakpoint should be hit exactly 2 times.
338 output
= self
.gdb
.c()
340 assertIn("Breakpoint ", output
)
341 assertIn("rot13 ", output
)
344 class Hwbp1(DebugTest
):
346 if self
.hart
.instruction_hardware_breakpoint_count
< 1:
347 return 'not_applicable'
349 if not self
.hart
.honors_tdata1_hmode
:
350 # Run to main before setting the breakpoint, because startup code
351 # will otherwise clear the trigger that we set.
355 self
.gdb
.hbreak("rot13")
356 # The breakpoint should be hit exactly 2 times.
358 output
= self
.gdb
.c()
360 assertRegexpMatches(output
, r
"[bB]reakpoint")
361 assertIn("rot13 ", output
)
364 class Hwbp2(DebugTest
):
366 if self
.hart
.instruction_hardware_breakpoint_count
< 2:
367 return 'not_applicable'
369 self
.gdb
.hbreak("main")
370 self
.gdb
.hbreak("rot13")
371 # We should hit 3 breakpoints.
372 for expected
in ("main", "rot13", "rot13"):
373 output
= self
.gdb
.c()
375 assertRegexpMatches(output
, r
"[bB]reakpoint")
376 assertIn("%s " % expected
, output
)
379 class TooManyHwbp(DebugTest
):
382 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
384 output
= self
.gdb
.c()
385 assertIn("Cannot insert hardware breakpoint", output
)
386 # Clean up, otherwise the hardware breakpoints stay set and future
388 self
.gdb
.command("D")
390 class Registers(DebugTest
):
392 # Get to a point in the code where some registers have actually been
397 # Try both forms to test gdb.
398 for cmd
in ("info all-registers", "info registers all"):
399 output
= self
.gdb
.command(cmd
)
400 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
401 assertIn(reg
, output
)
402 for line
in output
.splitlines():
403 assertRegexpMatches(line
, r
"^\S")
406 # mcpuid is one of the few registers that should have the high bit set
408 # Leave this commented out until gdb and spike agree on the encoding of
409 # mcpuid (which is going to be renamed to misa in any case).
410 #assertRegexpMatches(output, ".*mcpuid *0x80")
413 # The instret register should always be changing.
416 # instret = self.gdb.p("$instret")
417 # assertNotEqual(instret, last_instret)
418 # last_instret = instret
423 class UserInterrupt(DebugTest
):
425 """Sending gdb ^C while the program is running should cause it to
427 self
.gdb
.b("main:start")
430 self
.gdb
.c(wait
=False)
432 output
= self
.gdb
.interrupt()
433 assert "main" in output
434 assertGreater(self
.gdb
.p("j"), 10)
438 class InterruptTest(GdbSingleHartTest
):
439 compile_args
= ("programs/interrupt.c",)
441 def early_applicable(self
):
442 return self
.target
.supports_clint_mtime
449 output
= self
.gdb
.c()
450 assertIn(" main ", output
)
451 self
.gdb
.b("trap_entry")
452 output
= self
.gdb
.c()
453 assertIn(" trap_entry ", output
)
454 assertEqual(self
.gdb
.p("$mip") & 0x80, 0x80)
455 assertEqual(self
.gdb
.p("interrupt_count"), 0)
456 # You'd expect local to still be 0, but it looks like spike doesn't
457 # jump to the interrupt handler immediately after the write to
459 assertLess(self
.gdb
.p("local"), 1000)
460 self
.gdb
.command("delete breakpoints")
462 self
.gdb
.c(wait
=False)
465 interrupt_count
= self
.gdb
.p("interrupt_count")
466 local
= self
.gdb
.p("local")
467 if interrupt_count
> 1000 and \
471 assertGreater(interrupt_count
, 1000)
472 assertGreater(local
, 1000)
474 def postMortem(self
):
475 GdbSingleHartTest
.postMortem(self
)
476 self
.gdb
.p("*((long long*) 0x200bff8)")
477 self
.gdb
.p("*((long long*) 0x2004000)")
478 self
.gdb
.p("interrupt_count")
481 class MulticoreRegTest(GdbTest
):
482 compile_args
= ("programs/infinite_loop.S", "-DMULTICORE")
484 def early_applicable(self
):
485 return len(self
.target
.harts
) > 1
489 for hart
in self
.target
.harts
:
490 self
.gdb
.select_hart(hart
)
491 self
.gdb
.p("$pc=_start")
495 for hart
in self
.target
.harts
:
496 self
.gdb
.select_hart(hart
)
499 assertIn("main", self
.gdb
.where())
500 self
.gdb
.command("delete breakpoints")
502 # Run through the entire loop.
503 for hart
in self
.target
.harts
:
504 self
.gdb
.select_hart(hart
)
505 self
.gdb
.b("main_end")
507 assertIn("main_end", self
.gdb
.where())
510 for hart
in self
.target
.harts
:
511 self
.gdb
.select_hart(hart
)
512 # Check register values.
513 hart_id
= self
.gdb
.p("$x1")
514 assertNotIn(hart_id
, hart_ids
)
515 hart_ids
.append(hart_id
)
516 for n
in range(2, 32):
517 value
= self
.gdb
.p("$x%d" % n
)
518 assertEqual(value
, hart_ids
[-1] + n
- 1)
520 # Confirmed that we read different register values for different harts.
521 # Write a new value to x1, and run through the add sequence again.
523 for hart
in self
.target
.harts
:
524 self
.gdb
.select_hart(hart
)
525 self
.gdb
.p("$x1=0x%x" % (hart
.index
* 0x800))
526 self
.gdb
.p("$pc=main_post_csrr")
528 for hart
in self
.target
.harts
:
529 self
.gdb
.select_hart(hart
)
530 assertIn("main", self
.gdb
.where())
531 # Check register values.
532 for n
in range(1, 32):
533 value
= self
.gdb
.p("$x%d" % n
)
534 assertEqual(value
, hart
.index
* 0x800 + n
- 1)
536 class MulticoreRunHaltStepiTest(GdbTest
):
537 compile_args
= ("programs/multicore.c", "-DMULTICORE")
539 def early_applicable(self
):
540 return len(self
.target
.harts
) > 1
544 for hart
in self
.target
.harts
:
545 self
.gdb
.select_hart(hart
)
546 self
.gdb
.p("$pc=_start")
549 previous_hart_count
= [0 for h
in self
.target
.harts
]
550 previous_interrupt_count
= [0 for h
in self
.target
.harts
]
552 self
.gdb
.c(wait
=False)
557 self
.gdb
.p("$mstatus")
559 self
.gdb
.p("buf", fmt
="")
560 hart_count
= self
.gdb
.p("hart_count")
561 interrupt_count
= self
.gdb
.p("interrupt_count")
562 for i
, h
in enumerate(self
.target
.harts
):
563 assertGreater(hart_count
[i
], previous_hart_count
[i
])
564 assertGreater(interrupt_count
[i
], previous_interrupt_count
[i
])
565 self
.gdb
.select_hart(h
)
566 pc
= self
.gdb
.p("$pc")
568 stepped_pc
= self
.gdb
.p("$pc")
569 assertNotEqual(pc
, stepped_pc
)
571 class StepTest(GdbTest
):
572 compile_args
= ("programs/step.S", )
580 main_address
= self
.gdb
.p("$pc")
581 if self
.hart
.extensionSupported("c"):
582 sequence
= (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24)
584 sequence
= (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c)
585 for expected
in sequence
:
587 pc
= self
.gdb
.p("$pc")
588 assertEqual("%x" % (pc
- main_address
), "%x" % expected
)
590 class TriggerTest(GdbTest
):
591 compile_args
= ("programs/trigger.S", )
599 output
= self
.gdb
.c()
600 assertIn("Breakpoint", output
)
601 assertIn("_exit", output
)
603 class TriggerExecuteInstant(TriggerTest
):
604 """Test an execute breakpoint on the first instruction executed out of
607 main_address
= self
.gdb
.p("$pc")
608 self
.gdb
.command("hbreak *0x%x" % (main_address
+ 4))
610 assertEqual(self
.gdb
.p("$pc"), main_address
+4)
612 # FIXME: Triggers aren't quite working yet
613 #class TriggerLoadAddress(TriggerTest):
615 # self.gdb.command("rwatch *((&data)+1)")
616 # output = self.gdb.c()
617 # assertIn("read_loop", output)
618 # assertEqual(self.gdb.p("$a0"),
619 # self.gdb.p("(&data)+1"))
622 class TriggerLoadAddressInstant(TriggerTest
):
623 """Test a load address breakpoint on the first instruction executed out of
626 self
.gdb
.command("b just_before_read_loop")
628 read_loop
= self
.gdb
.p("&read_loop")
629 self
.gdb
.command("rwatch data")
631 # Accept hitting the breakpoint before or after the load instruction.
632 assertIn(self
.gdb
.p("$pc"), [read_loop
, read_loop
+ 4])
633 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
635 # FIXME: Triggers aren't quite working yet
636 #class TriggerStoreAddress(TriggerTest):
638 # self.gdb.command("watch *((&data)+3)")
639 # output = self.gdb.c()
640 # assertIn("write_loop", output)
641 # assertEqual(self.gdb.p("$a0"),
642 # self.gdb.p("(&data)+3"))
645 class TriggerStoreAddressInstant(TriggerTest
):
647 """Test a store address breakpoint on the first instruction executed out
649 self
.gdb
.command("b just_before_write_loop")
651 write_loop
= self
.gdb
.p("&write_loop")
652 self
.gdb
.command("watch data")
654 # Accept hitting the breakpoint before or after the store instruction.
655 assertIn(self
.gdb
.p("$pc"), [write_loop
, write_loop
+ 4])
656 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
658 class TriggerDmode(TriggerTest
):
659 def early_applicable(self
):
660 return self
.hart
.honors_tdata1_hmode
662 def check_triggers(self
, tdata1_lsbs
, tdata2
):
663 dmode
= 1 << (self
.hart
.xlen
-5)
667 if self
.hart
.xlen
== 32:
669 elif self
.hart
.xlen
== 64:
670 xlen_type
= 'long long'
672 raise NotImplementedError
677 tdata1
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
))
680 tdata2
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
+1))
685 assertEqual(tdata1
& 0xffff, tdata1_lsbs
)
686 assertEqual(tdata2
, tdata2
)
689 assertEqual(dmode_count
, 1)
694 self
.gdb
.command("hbreak write_load_trigger")
695 self
.gdb
.b("clear_triggers")
696 self
.gdb
.p("$pc=write_store_trigger")
697 output
= self
.gdb
.c()
698 assertIn("write_load_trigger", output
)
699 self
.check_triggers((1<<6) |
(1<<1), 0xdeadbee0)
700 output
= self
.gdb
.c()
701 assertIn("clear_triggers", output
)
702 self
.check_triggers((1<<6) |
(1<<0), 0xfeedac00)
704 class RegsTest(GdbTest
):
705 compile_args
= ("programs/regs.S", )
709 self
.gdb
.b("handle_trap")
712 class WriteGprs(RegsTest
):
714 regs
= [("x%d" % n
) for n
in range(2, 32)]
716 self
.gdb
.p("$pc=write_regs")
717 for i
, r
in enumerate(regs
):
718 self
.gdb
.p("$%s=%d" % (r
, (0xdeadbeef<<i
)+17))
719 self
.gdb
.p("$x1=data")
720 self
.gdb
.command("b all_done")
721 output
= self
.gdb
.c()
722 assertIn("Breakpoint ", output
)
724 # Just to get this data in the log.
725 self
.gdb
.command("x/30gx data")
726 self
.gdb
.command("info registers")
727 for n
in range(len(regs
)):
728 assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
729 ((0xdeadbeef<<n
)+17) & ((1<<self
.hart
.xlen
)-1))
731 class WriteCsrs(RegsTest
):
733 # As much a test of gdb as of the simulator.
734 self
.gdb
.p("$mscratch=0")
736 assertEqual(self
.gdb
.p("$mscratch"), 0)
737 self
.gdb
.p("$mscratch=123")
739 assertEqual(self
.gdb
.p("$mscratch"), 123)
741 self
.gdb
.p("$pc=write_regs")
742 self
.gdb
.p("$x1=data")
743 self
.gdb
.command("b all_done")
744 self
.gdb
.command("c")
746 assertEqual(123, self
.gdb
.p("$mscratch"))
747 assertEqual(123, self
.gdb
.p("$x1"))
748 assertEqual(123, self
.gdb
.p("$csr832"))
750 class DownloadTest(GdbTest
):
752 # pylint: disable=attribute-defined-outside-init
753 length
= min(2**10, self
.hart
.ram_size
- 2048)
754 self
.download_c
= tempfile
.NamedTemporaryFile(prefix
="download_",
755 suffix
=".c", delete
=False)
756 self
.download_c
.write("#include <stdint.h>\n")
757 self
.download_c
.write(
758 "unsigned int crc32a(uint8_t *message, unsigned int size);\n")
759 self
.download_c
.write("uint32_t length = %d;\n" % length
)
760 self
.download_c
.write("uint8_t d[%d] = {\n" % length
)
762 assert length
% 16 == 0
763 for i
in range(length
/ 16):
764 self
.download_c
.write(" /* 0x%04x */ " % (i
* 16))
766 value
= random
.randrange(1<<8)
767 self
.download_c
.write("0x%02x, " % value
)
768 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
769 self
.download_c
.write("\n")
770 self
.download_c
.write("};\n")
771 self
.download_c
.write("uint8_t *data = &d[0];\n")
772 self
.download_c
.write(
773 "uint32_t main() { return crc32a(data, length); }\n")
774 self
.download_c
.flush()
779 self
.binary
= self
.target
.compile(self
.hart
, self
.download_c
.name
,
780 "programs/checksum.c")
781 self
.gdb
.command("file %s" % self
.binary
)
785 self
.gdb
.command("b _exit")
786 self
.gdb
.c(timeout
=60)
787 assertEqual(self
.gdb
.p("status"), self
.crc
)
788 os
.unlink(self
.download_c
.name
)
790 #class MprvTest(GdbTest):
791 # compile_args = ("programs/mprv.S", )
796 # """Test that the debugger can access memory when MPRV is set."""
797 # self.gdb.c(wait=False)
799 # self.gdb.interrupt()
800 # output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)")
801 # assertIn("0xbead", output)
803 class PrivTest(GdbTest
):
804 compile_args
= ("programs/priv.S", )
806 # pylint: disable=attribute-defined-outside-init
809 misa
= self
.hart
.misa
810 self
.supported
= set()
812 self
.supported
.add(0)
814 self
.supported
.add(1)
816 self
.supported
.add(2)
817 self
.supported
.add(3)
819 class PrivRw(PrivTest
):
821 """Test reading/writing priv."""
822 # Disable physical memory protection by allowing U mode access to all
824 self
.gdb
.p("$pmpcfg0=0xf") # TOR, R, W, X
825 self
.gdb
.p("$pmpaddr0=0x%x" %
826 ((self
.hart
.ram
+ self
.hart
.ram_size
) >> 2))
828 # Leave the PC at _start, where the first 4 instructions should be
830 for privilege
in range(4):
831 self
.gdb
.p("$priv=%d" % privilege
)
833 actual
= self
.gdb
.p("$priv")
834 assertIn(actual
, self
.supported
)
835 if privilege
in self
.supported
:
836 assertEqual(actual
, privilege
)
838 class PrivChange(PrivTest
):
840 """Test that the core's privilege level actually changes."""
842 if 0 not in self
.supported
:
843 return 'not_applicable'
849 self
.gdb
.p("$priv=3")
850 main_address
= self
.gdb
.p("$pc")
852 assertEqual("%x" % self
.gdb
.p("$pc"), "%x" % (main_address
+4))
855 self
.gdb
.p("$priv=0")
857 # Should have taken an exception, so be nowhere near main.
858 pc
= self
.gdb
.p("$pc")
859 assertTrue(pc
< main_address
or pc
> main_address
+ 0x100)
863 parser
= argparse
.ArgumentParser(
864 description
="Test that gdb can talk to a RISC-V target.",
866 Example command line from the real world:
867 Run all RegsTest cases against a physical FPGA, with custom openocd command:
868 ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
870 targets
.add_target_options(parser
)
872 testlib
.add_test_run_options(parser
)
874 # TODO: remove global
875 global parsed
# pylint: disable=global-statement
876 parsed
= parser
.parse_args()
877 target
= targets
.target(parsed
)
878 testlib
.print_log_names
= parsed
.print_log_names
880 module
= sys
.modules
[__name__
]
882 return testlib
.run_all_tests(module
, target
, parsed
)
884 # TROUBLESHOOTING TIPS
885 # If a particular test fails, run just that one test, eg.:
886 # ./gdbserver.py MprvTest.test_mprv
887 # Then inspect gdb.log and spike.log to see what happened in more detail.
889 if __name__
== '__main__':