debug/targets/RISC-V/spike-1.cfg

   1 adapter_khz     10000
   2
   3 interface remote_bitbang
   4 remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
   5 remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
   6
   7 set _CHIPNAME riscv
   8 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
   9
  10 set _TARGETNAME $_CHIPNAME.cpu
  11 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
  12
  13 gdb_report_data_abort enable
  14
  15 # Expose an unimplemented CSR so we can test non-existent register access
  16 # behavior.
  17 riscv expose_csrs 2288
  18
  19 init
  20
  21 set challenge [ocd_riscv authdata_read]
  22 riscv authdata_write [expr $challenge + 1]
  23
  24 halt