debug/targets/RISC-V/spike-2.cfg

   1 # Connect to a mult-icore RISC-V target, exposing each hart as a thread.
   2 adapter_khz     10000
   3
   4 interface remote_bitbang
   5 remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
   6 remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
   7
   8 set _CHIPNAME riscv
   9 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
  10
  11 set _TARGETNAME_0 $_CHIPNAME.cpu0
  12 set _TARGETNAME_1 $_CHIPNAME.cpu1
  13 target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
  14 target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
  15
  16 gdb_report_data_abort enable
  17
  18 # Expose an unimplemented CSR so we can test non-existent register access
  19 # behavior.
  20 riscv expose_csrs 2288
  21
  22 init
  23
  24 set challenge [ocd_riscv authdata_read]
  25 riscv authdata_write [expr $challenge + 1]
  26
  27 targets $_TARGETNAME_0
  28 halt
  29 targets $_TARGETNAME_1
  30 halt