Make the debug tests aware of multicore.
[riscv-tests.git] / debug / targets / SiFive / Freedom / E300.py
1 import targets
2
3 class E300Hart(targets.Hart):
4 xlen = 32
5 ram = 0x80000000
6 ram_size = 256 * 1024 * 1024
7 instruction_hardware_breakpoint_count = 2
8 link_script_path = "Freedom.lds"
9
10 class E300(targets.Target):
11 openocd_config_path = "Freedom.cfg"
12 harts = [E300Hart()]