Merge pull request #123 from riscv/gdb_timeout
[riscv-tests.git] / debug / targets / SiFive / Freedom / E300Sim.py
1 import targets
2 import testlib
3
4 class E300Hart(targets.Hart):
5 xlen = 32
6 ram = 0x80000000
7 ram_size = 256 * 1024 * 1024
8 instruction_hardware_breakpoint_count = 2
9 link_script_path = "Freedom.lds"
10
11 class E300Sim(targets.Target):
12 timeout_sec = 6000
13 openocd_config_path = "Freedom.cfg"
14 harts = [E300Hart()]
15
16 def create(self):
17 return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)