Move target definition into individual files.
[riscv-tests.git] / debug / targets / SiFive / Freedom / U500Sim.py
1 class U500Sim(Target):
2 xlen = 64
3 timeout_sec = 6000
4 ram = 0x80000000
5 ram_size = 256 * 1024 * 1024
6 instruction_hardware_breakpoint_count = 2
7 openocd_config_path = "Freedom.cfg"
8 link_script_path = "Freedom.lds"
9
10 def target(self):
11 return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)