Use `gdb_report_register_access_error enable`
[riscv-tests.git] / debug / targets / SiFive / HiFive1.cfg
1 adapter_khz 10000
2
3 interface ftdi
4 ftdi_device_desc "Dual RS232-HS"
5 ftdi_vid_pid 0x0403 0x6010
6
7 ftdi_layout_init 0x0008 0x001b
8 ftdi_layout_signal nSRST -oe 0x0020
9
10 # ...
11
12 set _CHIPNAME riscv
13 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
14
15 set _TARGETNAME $_CHIPNAME.cpu
16 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
17 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
18 #-rtos riscv
19
20 gdb_report_data_abort enable
21 gdb_report_register_access_error enable
22
23 # Expose an unimplemented CSR so we can test non-existent register access
24 # behavior.
25 riscv expose_csrs 2288
26
27 flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
28 init
29 #reset
30 halt
31 flash protect 0 64 last off
32
33 echo "Ready for Remote Connections"